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| author | Jim Lawson | 2016-09-23 16:50:39 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-09-23 16:50:39 -0700 |
| commit | 3e174cc55be350a06e6e95ac6505a77167bd5a29 (patch) | |
| tree | 01813d93be83432a7c13fed6b1f56d9b9b942ca0 /chiselFrontend/src/main/scala/chisel3/core/Module.scala | |
| parent | 9c88d767e04ac25ab72380c39f30e39c83abf563 (diff) | |
| parent | 785620b1403d827986bf60c2a001d8d6f71eed72 (diff) | |
Merge branch 'master' into gsdt
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 9f7048cd..03e4f1b7 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -130,7 +130,7 @@ extends HasId { private[chisel3] def addId(d: HasId) { _ids += d } private[core] def ports: Seq[(String,Data)] = Vector( - ("clk", clock), ("reset", reset), ("io", io) + ("clock", clock), ("reset", reset), ("io", io) ) private[core] def computePorts: Seq[firrtl.Port] = { |