diff options
| author | Jim Lawson | 2016-08-29 09:33:51 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-08-29 09:33:51 -0700 |
| commit | 5fcdd12fe92bd22f9cdfb8f5e39e510684b709bf (patch) | |
| tree | d7b7d7c80bd5ab82c1b1d72e3a5eb28797d82304 /chiselFrontend/src/main/scala/chisel3/core/Module.scala | |
| parent | f84e6ef2d68404c741ea7e2aa2f3990ebb0984ee (diff) | |
Rename individual compile options.
Stricter values are "true". Current default (not strict) values are "false".
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 19063664..b4659a52 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -113,7 +113,7 @@ extends HasId { private[core] def computePorts: Seq[firrtl.Port] = { // If we're auto-wrapping IO definitions, do so now. - if (compileOptions.autoIOWrap && !ioDefined) { + if (!(compileOptions.requireIOWrap || ioDefined)) { IO(io) } for ((name, port) <- ports) yield { |