From 5fcdd12fe92bd22f9cdfb8f5e39e510684b709bf Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 09:33:51 -0700
Subject: Rename individual compile options. Stricter values are "true".
 Current default (not strict) values are "false".

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 19063664..b4659a52 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -113,7 +113,7 @@ extends HasId {
 
   private[core] def computePorts: Seq[firrtl.Port] = {
     // If we're auto-wrapping IO definitions, do so now.
-    if (compileOptions.autoIOWrap && !ioDefined) {
+    if (!(compileOptions.requireIOWrap || ioDefined)) {
       IO(io)
     }
     for ((name, port) <- ports) yield {
-- 
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