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path: root/chiselFrontend/src/main/scala/chisel3
AgeCommit message (Expand)Author
2020-03-25Rename subprojects to more canonical namesJack Koenig
2020-03-23Remove toNamed (and friends) deprecation. (#1377)Jim Lawson
2020-03-23Add NoChiselNamePrefix to ignore instances in @chiselName (#1383)Jack Koenig
2020-03-21Use innermost builder cause to trim stack trace (#1380)Schuyler Eldridge
2020-03-19Add Scaladoc to ChiselExceptionSchuyler Eldridge
2020-03-19Safer generation of ChiselException.builderNameSchuyler Eldridge
2020-03-19Code style improvementSchuyler Eldridge
2020-03-19Report trimmed stack trace of Builder causeSchuyler Eldridge
2020-03-06Make implicit clock and reset final vals (#1360)Jack Koenig
2020-03-06Provide API to set concrete type of implicit reset (#1361)Jack Koenig
2020-02-19Patch fix #1109 (#1346)Jack Koenig
2020-02-12Fix := of Reset and AsyncReset to DontCare (#1336)Jack Koenig
2020-02-11Clone child elements lazily in Vec (#1329)Jack Koenig
2020-02-10Printf: Add support for tabs, and give helpful error messages (#1323) (#1326)Jack Koenig
2020-02-06Emit FIRRTL andr, orr for Bits.{andR, orR}Schuyler Eldridge
2020-02-05Add information about widths to RegNext (#1318)Schuyler Eldridge
2020-02-03Add read-under-write parameter to SyncReadMem (#1183)Albert Magyar
2020-01-31Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-25Fixed code example typo in comment (#1294)Leway Colin
2020-01-25Remove redundancy code (#1296)Leway Colin
2020-01-23Minor changes - update comments, use MaxBitsBigIntToBigDecimal instead of '10...Jim Lawson
2020-01-22Update comment for Clock.asBool()Jim Lawson
2020-01-22Merge branch 'master' into add-asbool-to-clockChick Markley
2020-01-22Merge branch 'master' into big-decimal-methods-for-num-typesChick Markley
2020-01-22Change when/switch thunk type to Any (#1308)Schuyler Eldridge
2020-01-21Merge branch 'master' into big-decimal-methods-for-num-typeschick
2020-01-07Merge branch 'master' into add-asbool-to-clockJim Lawson
2020-01-07Remove over design (#1237)Leway Colin
2019-12-19Removed accidentally introduced parenschick
2019-12-18Add method asBool to Clock.chick
2019-12-18- New trait HasBinaryPoint which provides literal values as double and big de...chick
2019-12-17Merge branch 'master' into interval-fix-2Chick Markley
2019-12-17Band aid until litOption is implemented for Aggregates. (#1277)Jim Lawson
2019-12-12Fixed problem creating Interval literals with full rangeschick
2019-12-11- Change getPossibleValues of Interval to return a NumericRange former Seq ma...chick
2019-12-04Add ChiselEnum to BundleLiterals (#1215)Zhuanhao Wu
2019-12-02Fix asTypeOf for Clock (#1258)Jack Koenig
2019-11-29Fix deprecation warning that leaks into user code (#1256)Jack Koenig
2019-11-27Fix bidirectional Wire with Analog (#1252)Jack Koenig
2019-11-17Improve error message when assigning from Seq to Vec (#1239)Andrew Waterman
2019-11-15Enable @chiselName on non-module classes (#1209)John's Brew
2019-11-05Support literals cast to aggregates as async reset reg init values (#1225)Jack Koenig
2019-11-02Better anonymous and class-in-function desiredNameSchuyler Eldridge
2019-10-18Interval Data Type Support for Chisel (#1210)Chick Markley
2019-10-08Fix direction of dynamic index in complex Vec (#1196)Jack Koenig
2019-10-07Improve desiredName for nested objects/classesSchuyler Eldridge
2019-09-16Da steve101 tree reduce (#485)Jack Koenig
2019-09-11Move dontTouch, RawModule, and MultiIOModule out of experimental (#1162)Jim Lawson
2019-08-28refactor out _Factory traits + address EOF WSKamyar Mohajerani
2019-08-28Refactor Element, Num, and Analog classes to their own files (no functional c...Kamyar Mohajerani
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