diff options
| author | Jim Lawson | 2016-08-08 16:54:05 -0700 |
|---|---|---|
| committer | Donggyu Kim | 2016-08-16 11:26:42 -0700 |
| commit | e1e7c7ea3359df1351ba979287b62458e411e846 (patch) | |
| tree | 2460183946a0eca844e907a86accf1ee3c46789a /chiselFrontend/src/main/scala/chisel3/core/Module.scala | |
| parent | ddb7278760029be9d960ba8bf2b06ac8a8aac767 (diff) | |
Provide public SignalID trait to be used to conjure up a signal identifier.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/chisel3/core/Module.scala | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala index 5af744c4..4f25515b 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala @@ -63,6 +63,9 @@ extends HasId { /** Legalized name of this module. */ final val name = Builder.globalNamespace.name(desiredName) + /** Signal name (for simulation). */ + override def signalName(component: Component) = name + /** IO for this Module. At the Scala level (pre-FIRRTL transformations), * connections in and out of a Module may only go through `io` elements. */ |