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authorJim Lawson2016-07-27 09:13:45 -0700
committerJim Lawson2016-07-27 09:13:45 -0700
commite065416d59871d790cca9d75dc9a40fcc7b52015 (patch)
tree0d8c515233865db02595a4dc20c8a84b197294d3 /chiselFrontend/src/main/scala/chisel3/core/Module.scala
parentddeff65c1c50f0a7c3604cdc254538fbf1263d4f (diff)
Additional compatibility code.
Diffstat (limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')
-rw-r--r--chiselFrontend/src/main/scala/chisel3/core/Module.scala2
1 files changed, 2 insertions, 0 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index a593f539..ba0720a4 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -178,4 +178,6 @@ extends HasId {
_ids.foreach(_._onModuleClose)
this
}
+ // For debuggers/testers
+ lazy val getPorts = computePorts
}