5 files changed, 56 insertions, 5 deletions
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index ecae7340..6df85c6a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -33,10 +33,11 @@ abstract class Element(private[core] val width: Width) extends Data {
   private[core] def binding = _binding
 
   /** Return the binding for some bits. */
-  def dir: Direction = binding.direction.get
+  def dir: Direction = binding.direction.getOrElse(Direction.Unspecified)
 
   private[chisel3] final def allElements: Seq[Element] = Seq(this)
   def widthKnown: Boolean = width.known
+  def name: String = getRef.name
 }
 
 /** A data type for values represented by a single bitvector. Provides basic
@@ -709,6 +710,15 @@ object SInt {
     result.binding = LitBinding()
     result
   }
+  /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
+  def apply(direction: Direction, width: Int): SInt = {
+    val result = apply(Width(width))
+    direction match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
+  }
 }
 
 // REVIEW TODO: Why does this extend UInt and not Bits? Does defining airth
@@ -770,6 +780,15 @@ object Bool {
     result.binding = LitBinding()
     result
   }
+  /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+  def apply(direction: Direction): Bool = {
+    val result = apply()
+    direction match {
+      case Direction.Input => Input(result)
+      case Direction.Output => Output(result)
+      case Direction.Unspecified => result
+    }
+  }
 }
 
 object Mux {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index a593f539..ba0720a4 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -178,4 +178,6 @@ extends HasId {
     _ids.foreach(_._onModuleClose)
     this
   }
+  // For debuggers/testers
+  lazy val getPorts = computePorts
 }
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 926ca00d..5fcf5e67 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -7,6 +7,9 @@ package object chisel3 {
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
   import util.BitPat
 
+  import chisel3.core.{Binding, Bits, Element, FlippedBinder}
+  import chisel3.util._
+  import chisel3.internal.firrtl.Port
 
   type Direction = chisel3.core.Direction
   object Input {
@@ -117,4 +120,31 @@ package object chisel3 {
   val NODIR = chisel3.core.Direction.Unspecified
   type ChiselException = chisel3.internal.ChiselException
   type ValidIO[+T <: Data] = chisel3.util.Valid[T]
+  val Decoupled = chisel3.util.DecoupledIO
+
+  class EnqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
+    def init(): Unit = {
+      this.noenq()
+    }
+    override def cloneType: this.type = EnqIO(gen).asInstanceOf[this.type]
+  }
+  class DeqIO[+T <: Data](gen: T) extends DecoupledIO(gen) {
+    Binding.bind(this, FlippedBinder, "Error: Cannot flip ")
+    def init(): Unit = {
+      this.nodeq()
+    }
+    override def cloneType: this.type = DeqIO(gen).asInstanceOf[this.type]
+  }
+  object EnqIO {
+    def apply[T<:Data](gen: T): EnqIO[T] = new EnqIO(gen)
+  }
+  object DeqIO {
+    def apply[T<:Data](gen: T): DeqIO[T] = new DeqIO(gen)
+  }
+
+  // Debugger/Tester access to internal Chisel data structures and methods.
+  def getDataElements(a: Aggregate): Seq[Element] = {
+    a.allElements
+  }
+  def getModulePorts(m: Module): Seq[Port] = m.getPorts
 }
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
index cd8a5d63..d41c50e5 100644
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ b/src/test/scala/chiselTests/DeqIOSpec.scala
@@ -17,8 +17,8 @@ class UsesDeqIOInfo extends Bundle {
 
 class UsesDeqIO extends Module {
   val io = IO(new Bundle {
-    val in = DeqIO(new UsesDeqIOInfo)
-    val out = EnqIO(new UsesDeqIOInfo)
+    val in = chisel3.util.DeqIO(new UsesDeqIOInfo)
+    val out = chisel3.util.EnqIO(new UsesDeqIOInfo)
   })
 }
 
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index 6e1d267d..86c0d66f 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -28,8 +28,8 @@ class Packet extends Bundle {
   * The problem does not occur if the Vec is taken out
   */
 class VectorPacketIO(n: Int) extends Bundle {
-  val ins  = Vec(n, DeqIO(new Packet()))
-  val outs = Vec(n, EnqIO(new Packet()))
+  val ins  = Vec(n, chisel3.util.DeqIO(new Packet()))
+  val outs = Vec(n, chisel3.util.EnqIO(new Packet()))
 }
 
 /**