aboutsummaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)Author
2016-02-09Added chirrtl passes, need to update parserazidar
2016-02-09More bug fixesazidar
2016-02-09Added constprop,v-wrap,v-rename. All set to attempt like->like comparison of ↵azidar
rocketchip
2016-02-09Added Lower Types.azidar
2016-02-09Fixed Visitor incorrectly handling Vectors of UnknownWidth UInts and SIntsJack
2016-02-09Added Expand Whens passazidar
2016-02-09Adding ScalaTest for unit testing of Scala FIRRTL. Added a few basic tests ↵Jack
for the Parser. Added custom Parser exceptions for better error reporting and checking. Fixed bug in grammar not allowing most keywords as Ids
2016-02-09Fix bug in mem serializationJack
2016-02-09Fix start counting from 1 instead of 0 bugJack
2016-02-09Updated SInt/UInt emission to match stanza. Still need to update to new syntax.azidar
2016-02-09Fixed port emissionazidar
2016-02-09Moved passes to new packageazidar
2016-02-09Moved check-high-form to operate on working irazidar
2016-02-09Changed stanza output of UInt/SInt to include widths. Made tests match ↵azidar
accordingly
2016-02-09Added remove accessesazidar
2016-02-09Restructure passes to be new subpackage with more modular design, add new ↵Jack
structures Compiler and Emitter, deprecate old Passes object, update Driver to use new constructs
2016-02-09Fix serialize bugs: WSub(Field|Index|Access) printing extraneous w, module ↵Jack
not printing newline before ports
2016-02-09Added expand connect. Resolve now includes to working irazidar
2016-02-09Added resolve gendersazidar
2016-02-09WIP. Finished to working ir, resolve kinds, and infer typesazidar
2016-02-09WIP. Got to-working-ir workingazidar
2016-02-09WIP, nothing works. Starting creating working IR and necessary utilsazidar
2016-02-08Escape quotes in strings before emitting as VerilogPalmer Dabbelt
Without this we get failures with the current rocket-chip, when there are assertions with escaped strings in them.
2016-02-08Escape printf argument before emitting themPalmer Dabbelt
2016-01-29Fix no space after "flip" for flipped fields in Scala FIRRTL, also make ↵Jack
Scala FIRRTL emission match Stanza FIRRTL for bundles and regs
2016-01-29Changed reg syntax to new "with" semantics in Scala FIRRTLJack
2016-01-28Add support for single-line and multi-line scoping to Scala FIRRTL ↵Jack
preprocessing step. Also added with as scoping keyword
2016-01-28Fixed bug on translating SubAccess concrete syntax to abstract in Scala FIRRTLJack
2016-01-28WIP Added support for mux to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for is invalid and validif to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for stop to Scala FIRRTLjackkoenig
2016-01-28WIP Added support for printf to Scala FIRRTLjackkoenig
2016-01-28WIP: Added support for FIRRTL 0.2.0 Memories to Scala FIRRTLjackkoenig
2016-01-28Move IntLit ANTLR lexer rule to before String lexer rule to ensure IntLit of ↵jackkoenig
form "h..." is lexed as IntLit instead of String
2016-01-28Merge branch 'new-reg-prims' of github.com:ucb-bar/firrtlazidar
2016-01-28Fixed bug where subaccess indexes were being classified as female,azidar
mucking up the chirrtl->firrtl transform. #56.
2016-01-28Changed rmode to wmodeazidar
2016-01-28Use IsInvalid instead of Poisons in chirrtl -> firrtl transformazidar
2016-01-28Fixed bug where you cannot extract from a single bit wire in verilog. #55.azidar
2016-01-28Fixed bug where needed to cast bit-operation inputs prior to verilog emissionazidar
2016-01-28Added addw to working ir as an optimized verilog emissionazidar
2016-01-28Add map of symbol->symbol for wdefinstanceazidar
2016-01-28Fixed matching on types for and, or, and xorazidar
2016-01-28Fixed bug and updated test for changing mod to remazidar
2016-01-28Changed mod to remazidar
2016-01-28Updated with new primops. Removed addw,subw,quo,rem,bit. Added ↵azidar
head,tail,asClock.
2016-01-28Fixed readwriter syntax, and all printed mstats to use => instead of a colonazidar
2016-01-28Changed register syntax for optional reset and init valuesazidar
2016-01-27WIP Moving Scala FIRRTL to match spec 0.2.0. Not everything is implemented ↵jackkoenig
(notably stop, printf, mux, validif, ubits, sbits, readers, writers, and readwriters are incomplete)
2016-01-27Reworked readwriter typesazidar
generated by cgit v1.2.3 (git 2.25.1) at 2026-02-04 06:26:37 +0000