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authorPalmer Dabbelt2016-02-08 17:28:09 -0800
committerPalmer Dabbelt2016-02-08 17:28:09 -0800
commit9dbdb3c87e7ddb75ac937678763b177e0b095523 (patch)
tree34cb1c533657a5a066de2378e512bdc67a517a4f /src
parent23903d52f501e42ae7a633ad6509d9352cf2f68c (diff)
Escape quotes in strings before emitting as Verilog
Without this we get failures with the current rocket-chip, when there are assertions with escaped strings in them.
Diffstat (limited to 'src')
-rw-r--r--src/main/stanza/passes.stanza2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 60317a8e..75be008f 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2436,6 +2436,8 @@ defn escape (s:String) -> String :
for c in s do :
if c == '\n' :
add(s*,"\\n")
+ else if c == '"' :
+ add(s*, "\\\"")
else :
if c == 'x' and percent :
add(s*,"h")