From 9dbdb3c87e7ddb75ac937678763b177e0b095523 Mon Sep 17 00:00:00 2001
From: Palmer Dabbelt
Date: Mon, 8 Feb 2016 17:28:09 -0800
Subject: Escape quotes in strings before emitting as Verilog

Without this we get failures with the current rocket-chip, when there are
assertions with escaped strings in them.
---
 src/main/stanza/passes.stanza | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src')

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 60317a8e..75be008f 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2436,6 +2436,8 @@ defn escape (s:String) -> String :
    for c in s do :
       if c == '\n' :
          add(s*,"\\n")
+      else if c == '"' :
+         add(s*, "\\\"")
       else :
          if c == 'x' and percent :
             add(s*,"h")
-- 
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