Escape quotes in strings before emitting as Verilog

Without this we get failures with the current rocket-chip, when there are
assertions with escaped strings in them.

2 files changed, 20 insertions, 0 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 60317a8e..75be008f 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -2436,6 +2436,8 @@ defn escape (s:String) -> String :
    for c in s do :
       if c == '\n' :
          add(s*,"\\n")
+      else if c == '"' :
+         add(s*, "\\\"")
       else :
          if c == 'x' and percent :
             add(s*,"h")
diff --git a/test/passes/to-verilog/escape-quote.fir b/test/passes/to-verilog/escape-quote.fir
new file mode 100644
index 00000000..224026a9
--- /dev/null
+++ b/test/passes/to-verilog/escape-quote.fir
@@ -0,0 +1,18 @@
+; RUN: firrtl -i %s -o %s.v -X verilog ; cat %s.v | FileCheck %s
+
+;CHECK: module top(
+;CHECK:    input   clk
+;CHECK: );
+;CHECK:    always @(posedge clk) begin
+;CHECK:       `ifndef SYNTHESIS
+;CHECK:          if(1'h1) begin
+;CHECK:             $fwrite(32'h80000002,"This has an escaped quote (\") in it");
+;CHECK:          end
+;CHECK:       `endif
+;CHECK:    end
+;CHECK: endmodule
+
+circuit top :
+   module top :
+      input clk : Clock
+      printf(clk, UInt<1>(1), "This has an escaped quote (\") in it")