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authorJack2016-02-01 15:48:25 -0800
committerazidar2016-02-09 18:57:06 -0800
commit43ecab5aec6751d05ac986570e0648bb3d90982a (patch)
treec894f481e5076da1a7362e80d140b4bae4714028 /src
parent16e06109573ae8bff364bd0bdefd1af8ceb24c2e (diff)
Fix bug in mem serialization
Diffstat (limited to 'src')
-rw-r--r--src/main/scala/firrtl/Utils.scala5
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index 50d7b50b..be17c61e 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -700,9 +700,10 @@ object Utils {
case i: DefInstance => s"inst ${i.name} of ${i.module}"
case i: WDefInstance => s"inst ${i.name} of ${i.module}"
case m: DefMemory => {
- val str = new StringBuilder(s"mem ${m.name} : " + newline)
+ val str = new StringBuilder(s"mem ${m.name} : ")
withIndent {
- str ++= s"data-type => ${m.data_type}" + newline +
+ str ++= newline +
+ s"data-type => ${m.data_type.serialize}" + newline +
s"depth => ${m.depth}" + newline +
s"read-latency => ${m.read_latency}" + newline +
s"write-latency => ${m.write_latency}" + newline +