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2016-01-16WIP adding chirrtlazidar
2016-01-16WIP Almost there, need to generate enable connectionsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...azidar
2016-01-16WIP getting through testsazidar
2016-01-16Finished supporting nested accesses. Required some nuianced thinking. Pass al...azidar
2016-01-16WIP, hit semantic bug in WSubAccessazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
2016-01-16WIP. Compiles and almost done with verilog backend. Need to think about emitt...azidar
2016-01-16WIP. Compiles and there's some outputazidar
2016-01-16WIP. Compiles, need to testazidar
2016-01-16WIPazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2016-01-16Merge branch 'scala' of github.com:ucb-bar/firrtlazidar
2016-01-16Added some commentsazidar
2016-01-16Printf no longer adds a new lineazidar
2016-01-16shift right does not cast input as signedazidar
2016-01-16Extraction inputs are no longer castazidar
2016-01-16Width of multiply is sum of input widthsazidar
2016-01-16Removed print statementsazidar
2016-01-16Fixed inline-indexers bug where genders weren't properly calculated inazidar
2016-01-16Moved integer declaration inside module to be verilog (not system-verilog) co...Adam Izraelevitz
2016-01-16Stop now emits correct verilog to stop simulation, required passing a string ...azidar
2016-01-16Fixed bug in printf and stop to correctly print to STDERRazidar
2016-01-16Finished adding clocks to Stop and Printazidar
2015-12-11Add a renameall pass that renames nodes according to a user-providedPaul Rigge
2015-12-11Added LoFirrtl compiler, can be called with -X lofirrtlazidar
2015-12-08Refactored MIDAS code into its own repojackkoenig
2015-12-07Fixed bug, I think transformation works now for the most partjackkoenig
2015-12-07The transformation works! Kind of, it works fine when everything is alwasy re...jackkoenig
2015-12-06Working on generating SimTop, need to figure out how to split the top-level I...jackkoenig
2015-12-04Everything is broken, need Translator to work on files without a circuit, nee...jackkoenig
2015-12-03Some stylistic changes and a couple bugfixes to simulation wrapper generationjackkoenig
2015-12-03New wrapper generator completejackkoenig
2015-12-03Changing simwrapper to group ports that go to different places, not quite the...jackkoenig
2015-12-03Seem to be able to generate simulation wrapper module from DefInstjackkoenig
2015-12-02Added fame transformation and new package, making progressjackkoenig
2015-11-24In process of adding FAME-1 transformation, updated todos in grammar file, up...jackkoenig
2015-11-23Rename Test.scala to Driver.scalajackkoenig
2015-11-02Deleted extranous passes.stanza comments, updated standard passes. Added supp...jackkoenig
2015-10-30Added support for -b <backend> so that specific passes can be run then a back...jackkoenig
2015-10-19Merge pull request #47 from jackkoenig/masterAdam Izraelevitz
2015-10-15Reorganized Primops (renamed from PrimOps), added maps and functions to conve...Jack
2015-10-15Added infer-types pass, seems to work. Added infer-types error checking, modi...Jack
2015-10-14Modified getType to return Type rather than Option[Type] which makes more sen...Jack
2015-10-14Moved Logger to new private object DebugUtils, changed UInt/SInt value printi...Jack
2015-10-14Don't emit SystemVerilog keywordsAndrew Waterman
2015-10-12Added initial support for debug printing for lit based testing, most types of...Jack
2015-10-12Renamed Subindex to Index and added type information to Index and DoPrimOpJack
2015-10-12Added support for no width to mean unknown, and print nothing instead of <?> ...Jack
2015-10-12Added FIRRTL comment removal to TranslatorJack
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