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AgeCommit message (Expand)Author
2017-05-18Upgrade Logging facility (#488)Chick Markley
2017-05-17Make sure not to DCE input-only extmodules unless specified (#590)Jack Koenig
2017-05-12Bugfix: renaming instance ports was broken. (#588)Adam Izraelevitz
2017-05-11Improved Global Dead Code Elimination (#549)Jack Koenig
2017-05-10Update rename2 (#478)Adam Izraelevitz
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
2017-05-03Add test for source locators on multi-line reset registers (#554)Jack Koenig
2017-04-18"Scope" test resource (top.cpp). (#398)Jim Lawson
2017-04-03Find a single cycle from potentially many in a combinational SCCAlbert Magyar
2017-03-30Make force-append-anno-file work. Fixes #515 (#516)Jack Koenig
2017-03-29Fix bug where zero width expressions in nodes wouldn't get zeroed (#514)Jack Koenig
2017-03-23Add pass to detect combinational loopsAlbert Magyar
2017-03-23Pass now subclasses Transform (#477)Adam Izraelevitz
2017-03-23Add TargetDirAnnotation to give transforms access (#503)Jack Koenig
2017-03-22Fixed zero width perf bug #502Adam Izraelevitz
2017-03-22Fixing whitespace broke test....azidar
2017-03-22Bugfix: apply/unapply of PinAnnotation brokenazidar
2017-03-17Add utilites for digraphs and netlist analysesAlbert Magyar
2017-03-17Give better error message if missing emitedcircuitAdam Izraelevitz
2017-03-15Use newer rocket regression spec without comb loopAlbert Magyar
2017-03-09make sure infer-rw works for exclusive when statements (#481)Donggyu
2017-03-09Sint tests and change in serialization (#456)Adam Izraelevitz
2017-03-06Zero width (#402)Adam Izraelevitz
2017-03-06Fix mistake when rebasingAdam Izraelevitz
2017-03-06After merge, fixed added transformsAdam Izraelevitz
2017-03-06Added more stylized debugging styleAdam Izraelevitz
2017-03-06Addresses #459. Rewords transform annotations API.Adam Izraelevitz
2017-03-06Add ability to emit 1 file per module (#443)Jack Koenig
2017-03-03Bugfix: InlineInstances must prefix instancesAdam Izraelevitz
2017-03-01Allow nested digit fields in subfield expressionsJack Koenig
2017-03-01Fix bug in Lexer rule for DoubleLit and add testsJack Koenig
2017-02-26Align types and names of ports in emitted Verilog (#463)Jack Koenig
2017-02-23Add support for bundle fields to start with digits (#462)Jack Koenig
2017-02-21Implementation of nodedupe mem (#447)Colin Schmidt
2017-02-14Add support for Analog types in partial connect (#435)Jack Koenig
2017-02-14Fixes #441, ConvertFixedToSInt not recursing expsAdam Izraelevitz
2017-02-12Changed fixed-point cat semantics to return uint (#436)Adam Izraelevitz
2017-02-07Rework Attach to work on arbitrary Analog hierarchies (#415)Jack Koenig
2017-02-01Fix anno in backend (#428)Chick Markley
2017-02-01Fetch resource files as resources. (#399)Jim Lawson
2017-01-31Replace createTempDirectory with createTestDirectory (#427)Jack Koenig
2017-01-31Blackboxhelper (#418)Chick Markley
2017-01-29Keep firrtl's simulation environment in sync with chisel's. (#425)Jim Lawson
2017-01-27Fix signed types (#422)Angie Wang
2017-01-27Move BackendCompilationUtilities into a util package for use by chisel3. (#400)Jim Lawson
2017-01-23Add FixedType to uniqueify match statement.Paul Rigge
2017-01-20Remove merging of source locators during module deduplicationJack
2017-01-19Merge branch 'master' into addmiddlefirrtlcompilerJim Lawson
2017-01-19Verilog rem fix (#404)grebe
2017-01-19Merge branch 'master' into addmiddlefirrtlcompilerJim Lawson
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