diff options
| author | Jack Koenig | 2017-03-23 14:56:26 -0700 |
|---|---|---|
| committer | GitHub | 2017-03-23 14:56:26 -0700 |
| commit | 4cffd184397905eeb79e2df0913b4ded97dc8558 (patch) | |
| tree | 9b29a87132724aa02b445ff50977a1252b69e473 /src/test | |
| parent | 945d78448dc932290f89c271916fe8946aacb9c2 (diff) | |
Add TargetDirAnnotation to give transforms access (#503)
Also add GlobalCircuitAnnotation for creating similar annotations
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala new file mode 100644 index 00000000..60cbf0fc --- /dev/null +++ b/src/test/scala/firrtlTests/annotationTests/TargetDirAnnotationSpec.scala @@ -0,0 +1,71 @@ +// See LICENSE for license details. + +package firrtlTests +package annotationTests + +import firrtlTests._ +import firrtl._ + +/** Looks for [[TargetDirAnnotation]] */ +class FindTargetDirTransform(expected: String) extends Transform { + def inputForm = HighForm + def outputForm = HighForm + var foundTargetDir = false + var run = false + def execute(state: CircuitState): CircuitState = { + run = true + state.annotations.foreach { aMap => + aMap.annotations.collectFirst { + case TargetDirAnnotation(expected) => + foundTargetDir = true + } + } + state + } +} + +class TargetDirAnnotationSpec extends FirrtlFlatSpec { + behavior of "The target directory" + + val input = + """circuit Top : + | module Top : + | input foo : UInt<32> + | output bar : UInt<32> + | bar <= foo + """.stripMargin + val targetDir = "a/b/c" + + it should "be available as an annotation when using execution options" in { + val findTargetDir = new FindTargetDirTransform(targetDir) // looks for the annotation + + val optionsManager = new ExecutionOptionsManager("TargetDir") with HasFirrtlOptions { + commonOptions = commonOptions.copy(targetDirName = targetDir, + topName = "Top") + firrtlOptions = firrtlOptions.copy(compilerName = "high", + firrtlSource = Some(input), + customTransforms = Seq(findTargetDir)) + } + Driver.execute(optionsManager) + + // Check that FindTargetDirTransform transform is run and finds the annotation + findTargetDir.run should be (true) + findTargetDir.foundTargetDir should be (true) + + // Delete created directory + val dir = new java.io.File(targetDir) + dir.exists should be (true) + FileUtils.deleteDirectoryHierarchy("a") should be (true) + } + + it should "NOT be available as an annotation when using a raw compiler" in { + val findTargetDir = new FindTargetDirTransform(targetDir) // looks for the annotation + val compiler = new VerilogCompiler + val circuit = Parser.parse(input split "\n") + compiler.compileAndEmit(CircuitState(circuit, HighForm), Seq(findTargetDir)) + + // Check that FindTargetDirTransform does not find the annotation + findTargetDir.run should be (true) + findTargetDir.foundTargetDir should be (false) + } +} |
