diff options
| author | Adam Izraelevitz | 2017-05-12 13:59:36 -0700 |
|---|---|---|
| committer | GitHub | 2017-05-12 13:59:36 -0700 |
| commit | 23f1b8d1f9f94975fb5b4fe22f15343d853808d9 (patch) | |
| tree | db16def885630b32073794257ceab04d1b4624c9 /src/test | |
| parent | 1a9ac26f6a1b363ecd16f33a9c76e4275b3312d1 (diff) | |
Bugfix: renaming instance ports was broken. (#588)
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/AnnotationTests.scala | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala index 44964eba..e3dd3dbd 100644 --- a/src/test/scala/firrtlTests/AnnotationTests.scala +++ b/src/test/scala/firrtlTests/AnnotationTests.scala @@ -416,7 +416,7 @@ class AnnotationTests extends AnnotationSpec with Matchers { resultAnno should contain (anno("out_b_1")) } - ignore should "track deleted modules AND instances in dce" in { + "Renaming" should "track deleted modules AND instances in dce" in { val compiler = new VerilogCompiler val input = """circuit Top : @@ -445,6 +445,15 @@ class AnnotationTests extends AnnotationSpec with Matchers { anno("foo", mod = "DeadExt"), anno("bar", mod = "DeadExt") ) val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, getAMap(annos)), Nil) + /* Uncomment to help debug + println(result.circuit.serialize) + result.annotations.get.annotations.foreach{ a => + a match { + case DeletedAnnotation(xform, anno) => println(s"$xform deleted: ${a.target}") + case Annotation(target, _, _) => println(s"not deleted: $target") + } + } + */ val resultAnno = result.annotations.get.annotations resultAnno should contain (manno("Top")) |