Pass now subclasses Transform (#477)

8 files changed, 20 insertions, 30 deletions

diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index 77f07781..81d982e4 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -17,7 +17,7 @@ import org.scalatest.Matchers
  */
 trait AnnotationSpec extends LowTransformSpec {
   // Dummy transform
-  def transform = new CustomResolveAndCheck(LowForm)
+  def transform = new ResolveAndCheck
 
   // Check if Annotation Exception is thrown
   override def failingexecute(annotations: AnnotationMap, input: String): Exception = {
diff --git a/src/test/scala/firrtlTests/CInferMDirSpec.scala b/src/test/scala/firrtlTests/CInferMDirSpec.scala
index 773a0bf3..0d31038a 100644
--- a/src/test/scala/firrtlTests/CInferMDirSpec.scala
+++ b/src/test/scala/firrtlTests/CInferMDirSpec.scala
@@ -10,8 +10,6 @@ import annotations._
 
 class CInferMDir extends LowTransformSpec {
   object CInferMDirCheckPass extends Pass {
-    val name = "Check Enable Signal for Chirrtl Mems"
-
     // finds the memory and check its read port
     def checkStmt(s: Statement): Boolean = s match {
       case s: DefMemory if s.name == "indices" =>
@@ -38,10 +36,10 @@ class CInferMDir extends LowTransformSpec {
     }
   }
 
-  def transform = new PassBasedTransform {
+  def transform = new SeqTransform {
     def inputForm = LowForm
     def outputForm = LowForm
-    def passSeq = Seq(ConstProp, CInferMDirCheckPass)
+    def transforms = Seq(ConstProp, CInferMDirCheckPass)
   }
 
   "Memory" should "have correct mem port directions" in {
diff --git a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
index fd984661..c963c8ae 100644
--- a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
@@ -10,7 +10,6 @@ import annotations._
 
 class ChirrtlMemSpec extends LowTransformSpec {
   object MemEnableCheckPass extends Pass {
-    val name = "Check Enable Signal for Chirrtl Mems"
     type Netlist = collection.mutable.HashMap[String, Expression]
     def buildNetlist(netlist: Netlist)(s: Statement): Statement = {
       s match {
@@ -51,10 +50,10 @@ class ChirrtlMemSpec extends LowTransformSpec {
     }
   }
 
-  def transform = new PassBasedTransform {
+  def transform = new SeqTransform {
     def inputForm = LowForm
     def outputForm = LowForm
-    def passSeq = Seq(ConstProp, MemEnableCheckPass)
+    def transforms = Seq(ConstProp, MemEnableCheckPass)
   }
 
   "Sequential Memory" should "have correct enable signals" in {
diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index 3a20082f..d1ff6fd1 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -30,9 +30,8 @@ class CustomTransformSpec extends FirrtlFlatSpec {
     val delayModuleCircuit = parse(delayModuleString)
     val delayModule = delayModuleCircuit.modules.find(_.name == delayModuleCircuit.main).get
 
-    class ReplaceExtModuleTransform extends PassBasedTransform {
+    class ReplaceExtModuleTransform extends SeqTransform {
       class ReplaceExtModule extends Pass {
-        def name = "Replace External Module"
         def run(c: Circuit): Circuit = c.copy(
           modules = c.modules map {
             case ExtModule(_, "Delay", _, _, _) => delayModule
@@ -40,7 +39,7 @@ class CustomTransformSpec extends FirrtlFlatSpec {
           }
         )
       }
-      def passSeq = Seq(new ReplaceExtModule)
+      def transforms = Seq(new ReplaceExtModule)
       def inputForm = LowForm
       def outputForm = HighForm
     }
diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
index 73fdbe91..82c9d65f 100644
--- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala
+++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala
@@ -12,8 +12,9 @@ class InferReadWriteSpec extends SimpleTransformSpec {
   class InferReadWriteCheckException extends PassException(
     "Readwrite ports are not found!")
 
-  object InferReadWriteCheckPass extends Pass {
-    val name = "Check Infer ReadWrite Ports"
+  object InferReadWriteCheck extends Pass {
+    override def inputForm = MidForm
+    override def outputForm = MidForm
     def findReadWrite(s: Statement): Boolean = s match {
       case s: DefMemory if s.readLatency > 0 && s.readwriters.size == 1 =>
         s.name == "mem" && s.readwriters.head == "rw"
@@ -36,12 +37,6 @@ class InferReadWriteSpec extends SimpleTransformSpec {
     }
   }
 
-  class InferReadWriteCheck extends PassBasedTransform {
-    def inputForm = MidForm
-    def outputForm = MidForm
-    def passSeq = Seq(InferReadWriteCheckPass)
-  }
-
   def emitter = new MiddleFirrtlEmitter
   def transforms = Seq(
     new ChirrtlToHighFirrtl,
@@ -49,7 +44,7 @@ class InferReadWriteSpec extends SimpleTransformSpec {
     new ResolveAndCheck,
     new HighFirrtlToMiddleFirrtl,
     new memlib.InferReadWrite,
-    new InferReadWriteCheck
+    InferReadWriteCheck
   )
 
   "Infer ReadWrite Ports" should "infer readwrite ports for the same clock" in {
diff --git a/src/test/scala/firrtlTests/PassTests.scala b/src/test/scala/firrtlTests/PassTests.scala
index 589dfd38..e22fd513 100644
--- a/src/test/scala/firrtlTests/PassTests.scala
+++ b/src/test/scala/firrtlTests/PassTests.scala
@@ -35,17 +35,16 @@ abstract class SimpleTransformSpec extends FlatSpec with Matchers with Compiler
    }
 }
 
-class CustomResolveAndCheck(form: CircuitForm) extends PassBasedTransform {
-  private val wrappedTransform = new ResolveAndCheck
+class CustomResolveAndCheck(form: CircuitForm) extends SeqTransform {
   def inputForm = form
   def outputForm = form
-  def passSeq = wrappedTransform.passSeq
+  def transforms: Seq[Transform] = Seq[Transform](new ResolveAndCheck)
 }
 
 trait LowTransformSpec extends SimpleTransformSpec {
    def emitter = new LowFirrtlEmitter
    def transform: Transform
-   def transforms = Seq(
+   def transforms: Seq[Transform] = Seq(
       new ChirrtlToHighFirrtl(),
       new IRToWorkingIR(),
       new ResolveAndCheck(),
@@ -59,7 +58,7 @@ trait LowTransformSpec extends SimpleTransformSpec {
 trait MiddleTransformSpec extends SimpleTransformSpec {
    def emitter = new MiddleFirrtlEmitter
    def transform: Transform
-   def transforms = Seq(
+   def transforms: Seq[Transform] = Seq(
       new ChirrtlToHighFirrtl(),
       new IRToWorkingIR(),
       new ResolveAndCheck(),
@@ -75,7 +74,7 @@ trait HighTransformSpec extends SimpleTransformSpec {
    def transforms = Seq(
       new ChirrtlToHighFirrtl(),
       new IRToWorkingIR(),
-      new ResolveAndCheck(),
+      new CustomResolveAndCheck(HighForm),
       transform
    )
 }
diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index 1a5b44e6..0831bb31 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -18,10 +18,10 @@ class ReplSeqMemSpec extends SimpleTransformSpec {
     new InferReadWrite(),
     new ReplSeqMem(),
     new MiddleFirrtlToLowFirrtl(),
-    new PassBasedTransform {
+    new SeqTransform {
       def inputForm = LowForm
       def outputForm = LowForm
-      def passSeq = Seq(ConstProp, CommonSubexpressionElimination, DeadCodeElimination, RemoveEmpty)
+      def transforms = Seq(ConstProp, CommonSubexpressionElimination, DeadCodeElimination, RemoveEmpty)
     }
   )
 
diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
index ce591485..34a22c26 100644
--- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
@@ -178,10 +178,10 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
         |    io_out <= io_in
       """.stripMargin
 
-    class CheckChirrtlTransform extends PassBasedTransform {
+    class CheckChirrtlTransform extends SeqTransform {
       def inputForm = ChirrtlForm
       def outputForm = ChirrtlForm
-      val passSeq = Seq(passes.CheckChirrtl)
+      val transforms = Seq(passes.CheckChirrtl)
     }
 
     val chirrtlTransform = new CheckChirrtlTransform