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2015-08-18Fixed verilog emission from rand to randomazidar
2015-08-18Fixed bug in MinusWidth where it was adding instead of subtracting widthsazidar
2015-08-18Fixed so its length is greater than what it connects to. Changed shr to be ↵azidar
extract, not >>
2015-08-18Emit random initialization instead of zero initialization for Verilog regazidar
2015-08-17Removed leading zeros from UInt constantsazidar
2015-08-17Fixed bug where equality between expressions was incorrect, leading toazidar
an optimization that eliminated some when statements. Added test case.
2015-08-17Added tests for shl and mem. Fixed bug in verilog output of mem size.azidar
2015-08-05Added type inference before gender checkazidar
2015-08-05Fixed bug in temp elimination.azidar
2015-08-04Added check for reading from outputs with flipsazidar
2015-08-04Added () around width printersazidar
2015-08-04Added verilog keywords to uniquify themazidar
2015-08-04Fixed reading from instance's input ports. Fixed unique naming bug.azidar
2015-08-03Changed name mangling to use _ as a delin. Fixed bug in checking forazidar
invalid <> assignments.
2015-08-03Added concrete syntax for EmptyStmt()azidar
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect ↵azidar
indexed. Fixed various broken tests.
2015-07-31Fixed (?) resolve genders passazidar
2015-07-31Reading from output ports no longer causes errorsazidar
2015-07-31Fixed inferred type of bits and bitazidar
2015-07-31Fixed compiletime error, whooopsazidar
2015-07-31Allow bit operations on sintsazidar
2015-07-31Added errors for bulk connects where field names match but types/flips don'tazidar
2015-07-31Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-31Merge pull request #12 from ucb-bar/make-depsAdam Izraelevitz
Fix makefile dependences so make -j doesn't fail
2015-07-30Added module name to error messages.azidar
2015-07-30Merge branch 'new-low-firrtl'azidar
2015-07-30Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
2015-07-30Updated error and feature tests. Fixed bug in detecting incorrect gendersazidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Added primitive linking to firrtl-test-mainazidar
2015-07-30Started adding linking supportazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-29Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2015-07-29Updated frontend changesazidar
2015-07-29Added installation for linuxAdam Izraelevitz
2015-07-29Merge branch 'master' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
2015-07-29Fix makefile dependences so make -j doesn't failAndrew Waterman
2015-07-29Added linux zipAdam Izraelevitz
2015-07-29Finished supporting Chisel 2.0 Ref ChipAdam Izraelevitz
2015-07-29Add bigint support.Adam Izraelevitz
2015-07-28Integrated bigint. Mostly works, but getting "cast" error for make Test.Adam Izraelevitz
2015-07-23Updated specazidar
2015-07-22Fixed verilog so it emits non-random inital values. Changed Not to beAdam Izraelevitz
correct.
2015-07-22Minor updates to specazidar
2015-07-21Firrtl generates verilog that compiles, but does not workAdam Izraelevitz
2015-07-21Fixed bug in fix :Pazidar
2015-07-21Fixed removing non-referenced componentsazidar
2015-07-21Merge branch 'new-low-firrtl' of github.com:ucb-bar/firrtl into new-low-firrtlazidar
2015-07-21Updated TODOazidar
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