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| author | azidar | 2015-07-21 11:42:00 -0700 |
|---|---|---|
| committer | azidar | 2015-07-21 11:42:00 -0700 |
| commit | c093b68df9c461fb44306a1845bba7dc40d3136c (patch) | |
| tree | 50996c69ecd342d0559b2584c1d8f910a9d96279 | |
| parent | 98bb81d9d99150a80c77ed8f22d44748a02df628 (diff) | |
Updated TODO
| -rw-r--r-- | TODO | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -5,6 +5,7 @@ ======== Current Tasks ======== change parser to accept subword, but error --Merge with master +put clocks on accessors Tests: Lowering for instance types with bundle ports @@ -99,6 +100,10 @@ Firrtl interpreter (in scala) ======== Update Spec ======== Add explanation of an instance type, ie converting from input/output to default/reverse also, can only be used on the right side of := +Write a better conditional section +Improve node section +Add priority of connect statements to spec +Use source/sink instead of input/output Add assert statement explanation think about printfs think about subword on accessors, non-ground types @@ -133,6 +138,7 @@ Generate a ROM, and index with cycle counter, and dynamically check any wire on Variable size FIFOs TruthTable node Custom types? Parameterized Types? +Priority encoder/Log2 nodes ======== Next Layer Components ======= Accelerator with config registers |
