Added verilog keywords to uniquify them

5 files changed, 153 insertions, 43 deletions

diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index 812a917e..7ef942f2 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -198,7 +198,7 @@ defn emit-module (m:InModule,sh:HashTable<Symbol,Int>) :
 
 public defn emit-flo (with-output:(() -> False) -> False, c:Circuit) :
    with-output $ {
-      emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule,v-keywords))
+      emit-module(modules(c)[0] as InModule,get-sym-hash(modules(c)[0] as InModule))
       false
       }
    c
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 8cfd1541..3dd0585d 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -9,24 +9,6 @@ public defmulti print-debug (o:OutputStream, e:Expression|Stmt|Type|Port|Field|M
 
 ;============== GENSYM STUFF ======================
 
-public val v-keywords = to-list $ [
-    `always, `and, `assign, `attribute, `begin, `buf, `bufif0, `bufif1,
-    `case, `casex, `casez, `cmos, `deassign, `default, `defparam,
-    `disable, `edge, `else, `end, `endattribute, `endcase, `endfunction,
-    `endmodule, `endprimitive, `endspecify, `endtable, `endtask, `event,
-    `for, `force, `forever, `fork, `function, `highz0, `highz1, `if,
-    `ifnone, `initial, `inout, `input, `integer, `initvar, `join,
-    `medium, `module, `large, `macromodule, `nand, `negedge, `nmos,
-    `nor, `not, `notif0, `notif1, `or, `output, `parameter, `pmos,
-    `posedge, `primitive, `pull0, `pull1, `pulldown, `pullup, `rcmos,
-    `real, `realtime, `reg, `release, `repeat, `rnmos, `rpmos, `rtran,
-    `rtranif0, `rtranif1, `scalared, `signed, `small, `specify,
-    `specparam, `strength, `strong0, `strong1, `supply0, `supply1,
-    `table, `task, `time, `tran, `tranif0, `tranif1, `tri, `tri0,
-    `tri1, `triand, `trior, `trireg, `unsigned, `vectored, `wait,
-    `wand, `weak0, `weak1, `while, `wire, `wor, `xnor, `xor,
-    `SYNTHESIS, `PRINTF_COND, `VCS ]
-
 public defn firrtl-gensym (s:Symbol) -> Symbol :
    firrtl-gensym(s,HashTable<Symbol,Int>(symbol-hash))
 public defn firrtl-gensym (sym-hash:HashTable<Symbol,Int>) -> Symbol :
@@ -57,7 +39,7 @@ public defn firrtl-gensym (s:Symbol,sym-hash:HashTable<Symbol,Int>) -> Symbol :
 
 public defn get-sym-hash (m:InModule) -> HashTable<Symbol,Int> :
    get-sym-hash(m,list())
-public defn get-sym-hash (m:InModule,keywords:List<Symbol>) -> HashTable<Symbol,Int> :
+public defn get-sym-hash (m:InModule,keywords:Streamable<Symbol>) -> HashTable<Symbol,Int> :
    val sym-hash = HashTable<Symbol,Int>(symbol-hash)
    for k in keywords do :
       sym-hash[k] = 0
@@ -518,3 +500,117 @@ public defn pow (x:Long,y:Long) -> Long :
    x*
 
 
+;=================== VERILOG KEYWORDS =======================
+
+public val v-keywords = HashTable<Symbol,True>(symbol-hash)
+v-keywords[`always] = true
+v-keywords[`and] = true
+v-keywords[`assign] = true
+v-keywords[`attribute] = true
+v-keywords[`begin] = true
+v-keywords[`buf] = true
+v-keywords[`bufif0] = true
+v-keywords[`bufif1] = true
+v-keywords[`case] = true
+v-keywords[`casex] = true
+v-keywords[`casez] = true
+v-keywords[`cmos] = true
+v-keywords[`deassign] = true
+v-keywords[`default] = true
+v-keywords[`defparam] = true
+v-keywords[`disable] = true
+v-keywords[`edge] = true
+v-keywords[`else] = true
+v-keywords[`end] = true
+v-keywords[`endattribute] = true
+v-keywords[`endcase] = true
+v-keywords[`endfunction] = true
+v-keywords[`endmodule] = true
+v-keywords[`endprimitive] = true
+v-keywords[`endspecify] = true
+v-keywords[`endtable] = true
+v-keywords[`endtask] = true
+v-keywords[`event] = true
+v-keywords[`for] = true
+v-keywords[`force] = true
+v-keywords[`forever] = true
+v-keywords[`fork] = true
+v-keywords[`function] = true
+v-keywords[`highz0] = true
+v-keywords[`highz1] = true
+v-keywords[`if] = true
+v-keywords[`ifnone] = true
+v-keywords[`initial] = true
+v-keywords[`inout] = true
+v-keywords[`input] = true
+v-keywords[`integer] = true
+v-keywords[`initvar] = true
+v-keywords[`join] = true
+v-keywords[`medium] = true
+v-keywords[`module] = true
+v-keywords[`large] = true
+v-keywords[`macromodule] = true
+v-keywords[`nand] = true
+v-keywords[`negedge] = true
+v-keywords[`nmos] = true
+v-keywords[`nor] = true
+v-keywords[`not] = true
+v-keywords[`notif0] = true
+v-keywords[`notif1] = true
+v-keywords[`or] = true
+v-keywords[`output] = true
+v-keywords[`parameter] = true
+v-keywords[`pmos] = true
+v-keywords[`posedge] = true
+v-keywords[`primitive] = true
+v-keywords[`pull0] = true
+v-keywords[`pull1] = true
+v-keywords[`pulldown] = true
+v-keywords[`pullup] = true
+v-keywords[`rcmos] = true
+v-keywords[`real] = true
+v-keywords[`realtime] = true
+v-keywords[`reg] = true
+v-keywords[`release] = true
+v-keywords[`repeat] = true
+v-keywords[`rnmos] = true
+v-keywords[`rpmos] = true
+v-keywords[`rtran] = true
+v-keywords[`rtranif0] = true
+v-keywords[`rtranif1] = true
+v-keywords[`scalared] = true
+v-keywords[`signed] = true
+v-keywords[`small] = true
+v-keywords[`specify] = true
+v-keywords[`specparam] = true
+v-keywords[`strength] = true
+v-keywords[`strong0] = true
+v-keywords[`strong1] = true
+v-keywords[`supply0] = true
+v-keywords[`supply1] = true
+v-keywords[`table] = true
+v-keywords[`task] = true
+v-keywords[`time] = true
+v-keywords[`tran] = true
+v-keywords[`tranif0] = true
+v-keywords[`tranif1] = true
+v-keywords[`tri] = true
+v-keywords[`tri0] = true
+v-keywords[`tri1] = true
+v-keywords[`triand] = true
+v-keywords[`trior] = true
+v-keywords[`trireg] = true
+v-keywords[`unsigned] = true
+v-keywords[`vectored] = true
+v-keywords[`wait] = true
+v-keywords[`wand] = true
+v-keywords[`weak0] = true
+v-keywords[`weak1] = true
+v-keywords[`while] = true
+v-keywords[`wire] = true
+v-keywords[`wor] = true
+v-keywords[`xnor] = true
+v-keywords[`xor] = true
+v-keywords[`SYNTHESIS] = true
+v-keywords[`PRINTF_COND] = true
+v-keywords[`VCS] = true
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index e6d13196..2fc6847f 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -315,30 +315,43 @@ defn get-new-string (n:Char) -> String :
 
 defn remove-special-chars (c:Circuit) :
    defn rename (n:Symbol) -> Symbol :
-      val n* = Vector<String>()
+      val v = Vector<String>()
       for c in to-string(n) do :
-         add(n*,get-new-string(c))
-      symbol-join(n*)
+         add(v,get-new-string(c))
+      val n* = symbol-join(v)
+      if key?(v-keywords,n*) : 
+         symbol-join([n* `_])
+      else :
+         n*
    defn rename-t (t:Type) -> Type :
       match(t) :
          (t:BundleType) : BundleType $
             for f in fields(t) map :
                Field(rename(name(f)),flip(f),rename-t(type(f)))
-         (e) : map(rename-t,e)
+         (t:VectorType) : VectorType(rename-t(type(t)),size(t))
+         (t) : t
    defn rename-e (e:Expression) -> Expression :
       match(e) :
          (e:Ref) : Ref(rename(name(e)),rename-t(type(e)))
-         (e:Subfield) : Subfield(exp(e),rename(name(e)),rename-t(type(e)))
-         (e) : map(rename-t,map(rename-e,e))
+         (e:Subfield) : Subfield(rename-e(exp(e)),rename(name(e)),rename-t(type(e)))
+         (e:Index) : Index(rename-e(exp(e)),value(e),rename-t(type(e)))
+         (e:DoPrim) : DoPrim{op(e),_,consts(e),rename-t(type(e))} $ for x in args(e) map : rename-e(x)
+         (e:UIntValue) : e
+         (e:SIntValue) : e
    defn rename-s (s:Stmt) -> Stmt :
-      match(map(rename-e,s)) :
+      match(s) :
          (s:DefWire) : DefWire(info(s),rename(name(s)),rename-t(type(s)))
-         (s:DefRegister) : DefRegister(info(s),rename(name(s)),rename-t(type(s)),clock(s),reset(s))
-         (s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s))
-         (s:DefMemory) : DefMemory(info(s),rename(name(s)),rename-t(type(s)) as VectorType,seq?(s),clock(s))
-         (s:DefNode) : DefNode(info(s),rename(name(s)),value(s))
-         (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s))
-         (s) : map(rename-t,map(rename-s,s))
+         (s:DefRegister) : DefRegister(info(s),rename(name(s)),rename-t(type(s)),rename-e(clock(s)),rename-e(reset(s)))
+         (s:DefInstance) : DefInstance(info(s),rename(name(s)),rename-e(module(s)))
+         (s:DefMemory) : DefMemory(info(s),rename(name(s)),rename-t(type(s)) as VectorType,seq?(s),rename-e(clock(s)))
+         (s:DefNode) : DefNode(info(s),rename(name(s)),rename-e(value(s)))
+         (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),rename-e(source(s)),rename-e(index(s)),acc-dir(s))
+         (s:Conditionally) : Conditionally(info(s),rename-e(pred(s)),rename-s(conseq(s)),rename-s(alt(s)))
+         (s:Begin) : Begin $ for b in body(s) map : rename-s(b)
+         (s:OnReset) : OnReset(info(s),rename-e(loc(s)),rename-e(exp(s)))
+         (s:BulkConnect) : BulkConnect(info(s),rename-e(loc(s)),rename-e(exp(s)))
+         (s:Connect) : Connect(info(s),rename-e(loc(s)),rename-e(exp(s)))
+         (s:EmptyStmt) : s
 
    Circuit(info(c),modules*, rename(main(c))) where :
       val modules* =
@@ -1178,7 +1191,7 @@ defn expand-connect-indexed-stmt (s: Stmt,sh:HashTable<Symbol,Int>) -> Stmt :
 defn expand-connect-indexed (m: Module) -> Module :
    match(m) :
       (m:InModule) : 
-         val sh = get-sym-hash(m,v-keywords)
+         val sh = get-sym-hash(m,keys(v-keywords))
          InModule(info(m),name(m),ports(m),expand-connect-indexed-stmt(body(m),sh))
       (m:ExModule) : m
 
@@ -2204,7 +2217,7 @@ defn split-exp (c:Circuit) :
          match(m) :
             (m:InModule) :
                val v = Vector<Stmt>()
-               val sh = get-sym-hash(m,v-keywords)
+               val sh = get-sym-hash(m,keys(v-keywords))
                ;val before = current-time-us() - start-time
                ;println-all(["Before split: " before])
                split-exp-s(body(m),v,sh)
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index cbfd6d8b..aa755ed5 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -13,6 +13,7 @@ public defmethod name (b:Verilog) -> String : "To Verilog"
 public defmethod short-name (b:Verilog) -> String : "To Verilog"
 
 ;============ Utilz =============
+
 defn width! (w:Width) -> Long :
    match(w) : 
       (w:IntWidth) : to-long(width(w))
@@ -48,6 +49,12 @@ defn remove-subfield (e:Expression) -> Expression :
       (e:Subfield) : Ref(to-symbol $ string-join $ [emit(exp(e)) bundle-expand-delin name(e)],type(e))
       (e) : e
 
+defn get-name (e:Expression) -> Symbol :
+   match(e) :
+      (e:Ref) : name(e)
+      (e:Subfield) : error("Shouldn't be here")
+      (e) : error("Shouldn't be here")
+
 ;============ Verilog Backend =============
 
 defn emit-as-type (e:Expression,t:Type) -> String : 
@@ -150,12 +157,6 @@ defn emit (e:Expression) -> String :
                   v = concat(v, [" ^ " emit(x)])
                v
 
-defn get-name (e:Expression) -> Symbol :
-   match(e) :
-      (e:Ref) : name(e)
-      (e:Subfield) : error("Shouldn't be here")
-      (e) : error("Shouldn't be here")
-
 defn emit-module (m:InModule) :
    val vdecs = Vector<KeyValue<Symbol,Stmt>>() ; all declarations in order, to preserve ordering
    val decs = HashTable<Symbol,Stmt>(symbol-hash) ; all declarations, for fast lookups
diff --git a/test/errors/gender/InstancePorts.fir b/test/errors/gender/InstancePorts.fir
index d8d1355c..55d5fd46 100644
--- a/test/errors/gender/InstancePorts.fir
+++ b/test/errors/gender/InstancePorts.fir
@@ -8,10 +8,10 @@ circuit BTB :
     output out : UInt<1>
     out := in
   module BTB : 
-    input in : UInt<1>
+    input time : UInt<1>
     output out : UInt<1>
     
     inst queue of Queue
-    queue.in := in
+    queue.in := time
     out := queue.in