Fixed reading from instance's input ports. Fixed unique naming bug.

5 files changed, 54 insertions, 12 deletions

diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 5212bcb5..edb9928e 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -735,7 +735,7 @@ public defn check-genders (c:Circuit) -> Circuit :
          [MALE, FEMALE] : 
             add(errors,WrongGender(info,to-symbol(e),as-srcsnk(desired),as-srcsnk(gender)))
          [FEMALE, MALE] : 
-            if kind* != PortKind() :
+            if kind* != PortKind() and kind* != InstanceKind():
                add(errors,WrongGender(info,to-symbol(e),as-srcsnk(desired),as-srcsnk(gender)))
          else : false
 
@@ -801,7 +801,6 @@ public defn check-genders (c:Circuit) -> Circuit :
       match(m) :
          (m:ExModule) : false
          (m:InModule) : check-genders-s(body(m),genders)
-      println(genders)
    throw(PassExceptions(errors)) when not empty?(errors)
    c
 
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 2fb92407..8cfd1541 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -67,7 +67,11 @@ public defn get-sym-hash (m:InModule,keywords:List<Symbol>) -> HashTable<Symbol,
          s*[i] == '_' and digits?(substring(s*,i + 1))
       match(i*) :
          (i:False) : 
-            sym-hash[s] = 0
+            if key?(sym-hash,s) :
+               val num = sym-hash[s]
+               sym-hash[s] = max(num,0)
+            else :
+               sym-hash[s] = 0
          (i:Int) :
             val name = to-symbol(substring(s*,0,i))
             val digit = to-int(substring(s*,i + 1))
diff --git a/test/errors/gender/BulkWrong.fir b/test/errors/gender/BulkWrong.fir
index f65d0aa9..830e8156 100644
--- a/test/errors/gender/BulkWrong.fir
+++ b/test/errors/gender/BulkWrong.fir
@@ -1,16 +1,26 @@
 ; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
-; CHECK: Expression req is used as a sink but can only be used as a source.
+; CHECK: Expression in is used as a sink but can only be used as a source.
+; CHECK: Expression out.y is used as a sink but can only be used as a source.
+; CHECK: Expression in.y.z is used as a sink but can only be used as a source.
+; CHECK: Expression in.y.z is used as a sink but can only be used as a source.
 
 circuit BTB :
   module BTB : 
-    input clk : Clock
-    input reset : UInt<1>
-    input req : {valid : UInt<1>, bits : {addr : UInt<39>}}
+    input in : {x : UInt<1>, flip y : {flip z : UInt<1>}}
+    output out : {x : UInt<1>, flip y : {flip z : UInt<1>}}
 
-    output r : { x : UInt<1>, flip y : UInt<1>}
+    in <> out
+    out.y <> in.y
+    out.y.z <> in.y.z
+    
+    wire w : {x : UInt<1>, flip y : {flip z : UInt<1>}}
+    w <> in
+    in.y <> w.y
+    in.y.z <> w.y.z
 
-    wire x : {valid : UInt<1>, bits : {addr : UInt<39>}}
-    req <> x
+    w.x := addw(in.x,in.y.z)
+
+    out <> in
+    in.y <> out.y
+    in.y.z <> out.y.z
 
-    wire z : {x : UInt<1>, flip y : UInt<1> }
-    x.valid := r.x
diff --git a/test/errors/gender/InstancePorts.fir b/test/errors/gender/InstancePorts.fir
new file mode 100644
index 00000000..d8d1355c
--- /dev/null
+++ b/test/errors/gender/InstancePorts.fir
@@ -0,0 +1,17 @@
+; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK-NOT: Expression queue.in is used as a sink but can only be used as a source.
+; CHECK: Done!
+
+circuit BTB :
+  module Queue :
+    input in : UInt<1>
+    output out : UInt<1>
+    out := in
+  module BTB : 
+    input in : UInt<1>
+    output out : UInt<1>
+    
+    inst queue of Queue
+    queue.in := in
+    out := queue.in
+
diff --git a/test/errors/high-form/RemoveChar.fir b/test/errors/high-form/RemoveChar.fir
new file mode 100644
index 00000000..c9c2286e
--- /dev/null
+++ b/test/errors/high-form/RemoveChar.fir
@@ -0,0 +1,12 @@
+; RUN: firrtl -i %s -o %s.flo -X flo -p c 2>&1 | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit Top :
+  module Top :
+    wire x_1 : UInt<1>
+    x_1 := UInt(1)
+    wire x : UInt<1>
+    x := addw(addw(UInt(1),UInt(1)),UInt(1))
+
+
+