Fixed verilog so it emits non-random inital values. Changed Not to be

correct.

1 files changed, 5 insertions, 3 deletions

diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 50794eeb..6d9e2962 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -116,7 +116,7 @@ defn emit (e:Expression) -> String :
                match(type(args(e)[0])) :
                   (t:UIntType) : ["{1'b0," emit-as-type(args(e)[0],type(e)) "}"]
                   (t:SIntType) : [emit-as-type(args(e)[0],type(e))]
-            BIT-NOT-OP : ["!" emit-as-type(args(e)[0],type(e))]
+            BIT-NOT-OP : ["~ " emit-as-type(args(e)[0],type(e))]
             BIT-AND-OP : [emit-as-type(args(e)[0],type(e)) " & " emit-as-type(args(e)[1],type(e))]
             BIT-OR-OP : [emit-as-type(args(e)[0],type(e)) " | " emit-as-type(args(e)[1],type(e))]
             BIT-XOR-OP : [emit-as-type(args(e)[0],type(e)) " ^ " emit-as-type(args(e)[1],type(e))]
@@ -177,6 +177,7 @@ defn emit-module (m:InModule) :
    val inst-ports = HashTable<Symbol,Vector<Streamable>>(symbol-hash)
 
    val sh = get-sym-hash(m)
+   val rand-value = "0"
 
    for x in vdecs do :
       val sym = key(x)
@@ -196,11 +197,12 @@ defn emit-module (m:InModule) :
             else :
                add(my-clk-update,[sym " <= " emit(cons[sym]) ";"])
             updates[get-name(clock(s))] = my-clk-update
+            add(inits,[sym " = {" width!(type(s)) "{" rand-value "}};"])
          (s:DefMemory) :
             val vtype = type(s) as VectorType
             add(regs,["reg  " get-width(type(vtype)) " " sym " [0:" size(vtype) "];"])
             add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
-            add(inits,["  " sym "[initvar] = {" width!(type(vtype)) "{$random}};"])
+            add(inits,["  " sym "[initvar] = {" width!(type(vtype)) "{" rand-value "}};"])
          (s:DefNode) :
             add(wires,["wire " get-width(type(value(s))) " " sym ";"])
             add(assigns,["assign " sym " = " emit(value(s)) ";"])
@@ -221,7 +223,7 @@ defn emit-module (m:InModule) :
                      ; to make it sequential, register the index for an additional cycle
                      val index* = Ref(firrtl-gensym(name(index(s) as Ref),sh),type(index(s)))
                      add(regs,[ "reg  " get-width(type(index*)) " " name(index*) ";"]) 
-                     add(inits,[name(index*) " = {" width!(type(index*)) "{$random}};"])
+                     add(inits,[name(index*) " = {" width!(type(index*)) "{" rand-value "}};"])
                      val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector<Streamable>())
                      add(my-clk-update,[name(index*) " <= " emit(index(s)) ";"])
                      updates[get-name(clock(mem-declaration))] = my-clk-update