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2016-08-15Remove stanza (#231)Adam Izraelevitz
* Removed stanza implementation/tests. In the future we can move the stanza tests over, but for now they should be deleted. * Added back integration .fir files * Added Makefile to give Travis hooks * Added firrtl script (was ignored before)
2016-02-09Changed stanza output of UInt/SInt to include widths. Made tests match ↵azidar
accordingly
2016-01-28Fixed bug and updated test for changing mod to remazidar
2016-01-28Updated all tests to passazidar
2016-01-17BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed testsazidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16WIP getting through testsazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
Decided to not have Conditionally in low firrtl - instead, Print and Stop have enables
2015-09-30Fixed naming bug where __1 was matching. Caused lots o issues.azidar
2015-08-28Moved check type and check kind after check genderazidar
2015-08-24Changed all tests to use verilog backend.azidar
2015-08-19Fixed width inference bug where constraints were propagating backwards.azidar
Updated tests to match. #29.
2015-08-18Fixed so its length is greater than what it connects to. Changed shr to be ↵azidar
extract, not >>
2015-08-04Added check for reading from outputs with flipsazidar
2015-08-03Fixed performance bug in Split Expressions. Changed delin for connect ↵azidar
indexed. Fixed various broken tests.
2015-07-31Updated tests to pipe from stderr to stdoutazidar
2015-07-30Added eqv for bitwise equality, and change eq to be arithmetic equalityazidar
2015-07-30Updated lots of tests so they pass. Found one bug in expand whensazidar
2015-07-14Added tests for clocks. Added remove scope and special chars passes. Added ↵azidar
tests. Made more tests pass
2015-07-14Pass most tests. The ones that do not pass are not expected to, yetazidar
2015-07-14Still partial commit, many tests pass. Many tests fail.azidar
2015-05-18Big API Change. Pad is no longer supported. Widths of primops can be ↵azidar
flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
2015-05-15Updated firrtl for its passes to be a bit more modular, and to enable ↵azidar
plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.
2015-04-29Added dshl and dshrazidar
2015-04-28Instances are now male. Reworked lowering pass to be sane. ↵azidar
chisel3/ModuleVec.fir doesn't work because incorrecly generated?
2015-04-23Added new parser. Fixed all Tests. Added on-reset to parser, but don't ↵azidar
correctly handle it in compiler.
2015-04-20Fixed tests to use new execution arguments. Added and fixed chisel3 bugsazidar
2015-04-17Fixed bug in primop lowering during type inference. Added reduce ↵azidar
instructions and renamed concat -> cat, equal -> eq, and added neq and neg
2015-03-12Switched bundles from gender to flipazidar
2015-03-05Finished part of infer gender, tests not committedazidar
2015-03-04Finished infer-types passazidar
2015-03-03In-progress, working on inferring types passazidar
2015-02-25Added debug print statements to dump fields from nodes, and updated tests to ↵azidar
call firrtl correctly to enable/disable them
2015-02-24Rewrote README to include installation instructions and stanza ↵azidar
justification. Added response to feedback, locatd in notes/feedbackQA*. Use two different mains, one for testing and one for deployment (make build vs make build-deploy).
2015-02-24Updated tests, and included a check for the name of the pass, whichazidar
allows the compiler to print after each pass to ease debugging