| Age | Commit message (Expand) | Author |
|---|
| 2016-08-15 | Remove stanza (#231) | Adam Izraelevitz |
| 2016-02-09 | Changed stanza output of UInt/SInt to include widths. Made tests match accord... | azidar |
| 2016-01-28 | Fixed bug and updated test for changing mod to rem | azidar |
| 2016-01-28 | Updated all tests to pass | azidar |
| 2016-01-17 | BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed tests | azidar |
| 2016-01-16 | Fixed all tests so they either pass are marked as expected failures | azidar |
| 2016-01-16 | WIP getting through tests | azidar |
| 2016-01-16 | New memory works with verilog. Slowly changing tests and fixing bugs. | azidar |
| 2015-09-30 | Fixed naming bug where __1 was matching. Caused lots o issues. | azidar |
| 2015-08-28 | Moved check type and check kind after check gender | azidar |
| 2015-08-24 | Changed all tests to use verilog backend. | azidar |
| 2015-08-19 | Fixed width inference bug where constraints were propagating backwards. | azidar |
| 2015-08-18 | Fixed so its length is greater than what it connects to. Changed shr to be e... | azidar |
| 2015-08-04 | Added check for reading from outputs with flips | azidar |
| 2015-08-03 | Fixed performance bug in Split Expressions. Changed delin for connect indexed... | azidar |
| 2015-07-31 | Updated tests to pipe from stderr to stdout | azidar |
| 2015-07-30 | Added eqv for bitwise equality, and change eq to be arithmetic equality | azidar |
| 2015-07-30 | Updated lots of tests so they pass. Found one bug in expand whens | azidar |
| 2015-07-14 | Added tests for clocks. Added remove scope and special chars passes. Added te... | azidar |
| 2015-07-14 | Pass most tests. The ones that do not pass are not expected to, yet | azidar |
| 2015-07-14 | Still partial commit, many tests pass. Many tests fail. | azidar |
| 2015-05-18 | Big API Change. Pad is no longer supported. Widths of primops can be flexible... | azidar |
| 2015-05-15 | Updated firrtl for its passes to be a bit more modular, and to enable pluggin... | azidar |
| 2015-04-29 | Added dshl and dshr | azidar |
| 2015-04-28 | Instances are now male. Reworked lowering pass to be sane. chisel3/ModuleVec.... | azidar |
| 2015-04-23 | Added new parser. Fixed all Tests. Added on-reset to parser, but don't correc... | azidar |
| 2015-04-20 | Fixed tests to use new execution arguments. Added and fixed chisel3 bugs | azidar |
| 2015-04-17 | Fixed bug in primop lowering during type inference. Added reduce instructions... | azidar |
| 2015-03-12 | Switched bundles from gender to flip | azidar |
| 2015-03-05 | Finished part of infer gender, tests not committed | azidar |
| 2015-03-04 | Finished infer-types pass | azidar |
| 2015-03-03 | In-progress, working on inferring types pass | azidar |
| 2015-02-25 | Added debug print statements to dump fields from nodes, and updated tests to ... | azidar |
| 2015-02-24 | Rewrote README to include installation instructions and stanza justification.... | azidar |
| 2015-02-24 | Updated tests, and included a check for the name of the pass, which | azidar |
