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AgeCommit message (Expand)Author
2016-08-15Remove stanza (#231)Adam Izraelevitz
2016-02-24Fixed printf bugs in scala and stanza versions. Required special casing print...Adam Izraelevitz
2016-02-09Merge branch 'master' of github.com:ucb-bar/firrtlazidar
2016-02-09Changed stanza output of UInt/SInt to include widths. Made tests match accord...azidar
2016-02-08Escape quotes in strings before emitting as VerilogPalmer Dabbelt
2016-01-28Fixed rdwr and wr to verilog testsazidar
2016-01-28Fixed bug where subaccess indexes were being classified as female,azidar
2016-01-28Changed rmode to wmodeazidar
2016-01-28Added tests for previous commitazidar
2016-01-28Added addw to working ir as an optimized verilog emissionazidar
2016-01-28Fixed bug and updated test for changing mod to remazidar
2016-01-28Updated all tests to passazidar
2016-01-27Fixed additional tests and inferring rdwr ports in chirrtljackkoenig
2016-01-25Fixed bug where poisons were not being declaredazidar
2016-01-25Added isinvalid and validifazidar
2016-01-25Fixed support for muxes and nodes with passive aggregate typesazidar
2016-01-25Changed tests to pass with change to postfix of generated nameazidar
2016-01-24Fixed tests that broke from changing verilog backend and removing mask from w...azidar
2016-01-24Added DefMemory to CInfer Typesazidar
2016-01-17BIT-AND, BIT-OR, and BIT-XOR now can accept SInts. Fixed testsazidar
2016-01-16Added a bunch of tests and added firrtl-stanza and firrtl-scala to .gitignoreazidar
2016-01-16Fixed all tests so they either pass are marked as expected failuresazidar
2016-01-16Updated passes so they test new-memazidar
2016-01-16Fixed a testazidar
2016-01-16Finished first cut at new firrtl - time for testing! Chirrtl requires masks t...azidar
2016-01-16Fixed a bunch of tests, and minor bugsazidar
2016-01-16WIP. Fixed a bunch of tests. Starting on implementing chirrtl, but hit roadbl...azidar
2016-01-16WIP getting through testsazidar
2016-01-16New memory works with verilog. Slowly changing tests and fixing bugs.azidar
2016-01-16WIP. Compiles and almost done with verilog backend. Need to think about emitt...azidar
2016-01-16WIPazidar
2016-01-16WIP need to correctly output readwrite portsazidar
2016-01-16Fixed inline-indexers bug where genders weren't properly calculated inazidar
2015-10-01Merge pull request #43 from ucb-bar/new-semanticsAndrew Waterman
2015-10-01Change of FIRRTL semantics!azidar
2015-09-30Fixed test so it passes, as it shouldazidar
2015-09-30Made simple9.fir a short, more isolated test caseazidar
2015-09-30Moved To-Real-Ir earlier, so CheckWidth could happen before PadWidthazidar
2015-09-30Fixed naming bug where __1 was matching. Caused lots o issues.azidar
2015-09-29Fixed final bug. All tests pass. Accessors are a go.azidar
2015-09-29Added DecToIndexer/DecFromIndexer. Fixed most use cases of incorrect catching...azidar
2015-08-28Moved check type and check kind after check genderazidar
2015-08-25Fixed bug in split expression that leaked connect statements out of a conditi...azidar
2015-08-24Changed all tests to use verilog backend.azidar
2015-08-20Added tests, cleaned up repoazidar
2015-08-20Added rsh test for const-propazidar
2015-08-19Added new const propagation testazidar
2015-08-19Fixed width inference bug where constraints were propagating backwards.azidar
2015-08-18Updated shr test so it is an expected passazidar
2015-08-18Fixed so its length is greater than what it connects to. Changed shr to be e...azidar
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