diff options
| author | azidar | 2016-01-25 15:34:32 -0800 |
|---|---|---|
| committer | azidar | 2016-01-25 15:34:32 -0800 |
| commit | 25131f76567f92f18a46c41156f3a88b319591de (patch) | |
| tree | eaa8fa27be8daac6649b9554df600cc2f8b1468c /test/passes | |
| parent | 63928c30dbf074deed522fb99099b4d82c07b602 (diff) | |
Added isinvalid and validif
Diffstat (limited to 'test/passes')
| -rw-r--r-- | test/passes/pull-muxes/Muxes.fir | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/test/passes/pull-muxes/Muxes.fir b/test/passes/pull-muxes/Muxes.fir new file mode 100644 index 00000000..295e3ca0 --- /dev/null +++ b/test/passes/pull-muxes/Muxes.fir @@ -0,0 +1,17 @@ +; RUN: firrtl -i %s -o %s.v -X verilog -p c 2>&1 | tee %s.out | FileCheck %s +circuit Top : + module Top : + input a : {f:UInt<3>[3]}[2] + input b : {f:UInt<3>[3]}[2] + input p : UInt<1> + input i : UInt<1> + node x = mux(p,mux(p,a[i],a[1]).f,b[i].f)[2] + + + +;CHECK: Pull Muxes +;CHECK: node x = mux(p, mux(p, a[i].f[2], a[1].f[2]), b[i].f[2]) +;CHECK: Finished Pull Muxes +;CHECK: Done! + + |
