diff options
| author | azidar | 2015-07-07 10:13:29 -0700 |
|---|---|---|
| committer | azidar | 2015-07-14 11:29:55 -0700 |
| commit | d696dd01de8a1a83a376c719490f475be991f387 (patch) | |
| tree | ca5d8f21c0f7787cc6eb00e078f0c0ae1e20a182 /test/passes/infer-types | |
| parent | 3c8f283b445ca99d4ed4c1e04e2bc8bdcdbd72f6 (diff) | |
Pass most tests. The ones that do not pass are not expected to, yet
Diffstat (limited to 'test/passes/infer-types')
| -rw-r--r-- | test/passes/infer-types/bundle.fir | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir index 892103d2..6309b46f 100644 --- a/test/passes/infer-types/bundle.fir +++ b/test/passes/infer-types/bundle.fir @@ -4,9 +4,21 @@ circuit top : module top : wire z : { x : UInt, flip y: SInt} + z.x := UInt(1) + z.y := SInt(1) node x = z.x ;CHECK: node x = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.x@<t:UInt> node y = z.y ;CHECK: node y = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.y@<t:SInt> wire a : UInt<3>[10] ;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt<3>[10]@<t:UInt>> + a[0] := UInt(1) + a[1] := UInt(1) + a[2] := UInt(1) + a[3] := UInt(1) + a[4] := UInt(1) + a[5] := UInt(1) + a[6] := UInt(1) + a[7] := UInt(1) + a[8] := UInt(1) + a[9] := UInt(1) node b = a[2] ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt> read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt(3)] ; CHECK: Finished Infer Types |