New memory works with verilog. Slowly changing tests and fixing bugs.

Decided to not have Conditionally in low firrtl - instead, Print and
Stop have enables

3 files changed, 39 insertions, 39 deletions

diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index 89f9ac22..400aecde 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -4,21 +4,21 @@
 circuit top :
    module top :
       wire z : { x : UInt, flip y: SInt}
-      z.x := UInt(1)
-      z.y := SInt(1)
+      z.x <= UInt(1)
+      z.y <= SInt(1)
       node x = z.x            ;CHECK: node x = z@<t:{ x : UInt, flip y : SInt}>.x@<t:UInt>
       node y = z.y            ;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt>
       wire a : UInt<3>[10]    ;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt<3>[10]@<t:UInt>>
-      a[0] := UInt(1)
-      a[1] := UInt(1)
-      a[2] := UInt(1)
-      a[3] := UInt(1)
-      a[4] := UInt(1)
-      a[5] := UInt(1)
-      a[6] := UInt(1)
-      a[7] := UInt(1)
-      a[8] := UInt(1)
-      a[9] := UInt(1)
+      a[0] <= UInt(1)
+      a[1] <= UInt(1)
+      a[2] <= UInt(1)
+      a[3] <= UInt(1)
+      a[4] <= UInt(1)
+      a[5] <= UInt(1)
+      a[6] <= UInt(1)
+      a[7] <= UInt(1)
+      a[8] <= UInt(1)
+      a[9] <= UInt(1)
       node b = a[2]           ;CHECK: node b = a@<t:UInt<3>[10]@<t:UInt>>[2]@<t:UInt>
       read accessor c = a[UInt(3)] ;CHECK: read accessor c = a@<t:UInt<3>[10]@<t:UInt>>[UInt("h3")@<t:UInt>]
 ; CHECK: Finished Infer Types
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 24860b91..68ec4174 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -6,8 +6,8 @@ circuit top :
       input x : UInt
       input y : UInt
       output z : UInt
-      z := subw(x, y)
-      ;CHECK: z@<t:UInt> := subw(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
+      z <= subw(x, y)
+      ;CHECK: z@<t:UInt> <= subw(x@<t:UInt>, y@<t:UInt>)@<t:UInt>
    module gcd :
       input a : UInt<16>
       input b : UInt<16>
@@ -19,27 +19,27 @@ circuit top :
       reg x : UInt,clk,reset
       reg y : UInt,clk,reset
 ; CHECK: reg x : UInt, clk@<t:Clock>, reset@<t:UInt>@<t:UInt>
-      onreset x := UInt(0)
-      onreset y := UInt(42)
+      onreset x <= UInt(0)
+      onreset y <= UInt(42)
       when gt(x, y) :
       ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
          inst s of subtracter
          ;CHECK: inst s of subtracter@<t:{flip x : UInt, flip y : UInt,  z : UInt}>
-         s.x := x
-         s.y := y
-         x := s.z
-         ;CHECK: s@<t:{flip x : UInt, flip y : UInt,  z : UInt}>.x@<t:UInt> := x@<t:UInt>
-         ;CHECK: s@<t:{flip x : UInt, flip y : UInt,  z : UInt}>.y@<t:UInt> := y@<t:UInt>
-         ;CHECK: x@<t:UInt> := s@<t:{flip x : UInt, flip y : UInt,  z : UInt}>.z@<t:UInt>      
+         s.x <= x
+         s.y <= y
+         x <= s.z
+         ;CHECK: s@<t:{flip x : UInt, flip y : UInt,  z : UInt}>.x@<t:UInt> <= x@<t:UInt>
+         ;CHECK: s@<t:{flip x : UInt, flip y : UInt,  z : UInt}>.y@<t:UInt> <= y@<t:UInt>
+         ;CHECK: x@<t:UInt> <= s@<t:{flip x : UInt, flip y : UInt,  z : UInt}>.z@<t:UInt>      
       else :
          inst s2 of subtracter
-         s2.x := x
-         s2.y := y
-         y := s2.z
+         s2.x <= x
+         s2.y <= y
+         y <= s2.z
       when e :
-         x := a
-         y := b
-      z := x
+         x <= a
+         y <= b
+      z <= x
    module top :
       input a : UInt<16>
       input b : UInt<16>
@@ -47,11 +47,11 @@ circuit top :
       input reset : UInt<1>
       output z : UInt
       inst i of gcd
-      i.a := a
-      i.b := b
-      i.clk := clk
-      i.reset := reset
-      i.e := UInt(1)
-      z := i.z
+      i.a <= a
+      i.b <= b
+      i.clk <= clk
+      i.reset <= reset
+      i.e <= UInt(1)
+      z <= i.z
 
 ; CHECK: Finished Infer Types
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index ac057c68..102a94ae 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -9,11 +9,11 @@ circuit top :
       wire d : SInt<8>
       wire e : UInt<1>
 
-      a := UInt(1)
-      b := UInt(1)
-      c := SInt(1)
-      d := SInt(1)
-      e := UInt(1)
+      a <= UInt(1)
+      b <= UInt(1)
+      c <= SInt(1)
+      d <= SInt(1)
+      e <= UInt(1)
 
       node vadd = add(a, c)    ;CHECK: node vadd = add(a@<t:UInt>, c@<t:SInt>)@<t:SInt>
       node wadd = add(a, b) ;CHECK: node wadd = add(a@<t:UInt>, b@<t:UInt>)@<t:UInt>