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authorazidar2015-05-15 16:34:34 -0700
committerazidar2015-05-15 16:34:34 -0700
commit2702e571040e7a07317b79f9c5cfdbd61b9ab2bf (patch)
tree0e5973d175be18851865b712e16871764157889f /test/passes/infer-types
parent521a4277bfc1d764dc9ee771c604200525e871cb (diff)
Updated firrtl for its passes to be a bit more modular, and to enable plugging in other backends. Also updated a lot of tests, but not all of them because its annoying.
Diffstat (limited to 'test/passes/infer-types')
-rw-r--r--test/passes/infer-types/bundle.fir4
-rw-r--r--test/passes/infer-types/gcd.fir2
-rw-r--r--test/passes/infer-types/primops.fir2
3 files changed, 4 insertions, 4 deletions
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index cde9be6d..5018aeef 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -1,8 +1,8 @@
-; RUN: firrtl -i %s -o %s.flo -x abcde -p ct | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p ct | tee %s.out | FileCheck %s
;CHECK: Infer Types
circuit top :
- module subtracter :
+ module top :
wire z : { x : UInt, flip y: SInt}
node x = z.x ;CHECK: node x = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.x@<t:UInt>
node y = z.y ;CHECK: node y = z@<t:{ x : UInt@<t:UInt>, flip y : SInt@<t:SInt>}>.y@<t:SInt>
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index 6e3109a5..23d92b4f 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcde -p ct | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p ct | tee %s.out | FileCheck %s
;CHECK: Infer Types
circuit top :
diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir
index 589ab546..e0022cfb 100644
--- a/test/passes/infer-types/primops.fir
+++ b/test/passes/infer-types/primops.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcde -p ct | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -X flo -p ct | tee %s.out | FileCheck %s
;CHECK: Infer Types
circuit top :