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authorazidar2016-01-31 12:59:31 -0800
committerazidar2016-02-09 18:57:06 -0800
commite985d47312458459e9ebe42fe99b5a063c08e637 (patch)
treed726c711e86d6e948a220a568dcae0a997629d18 /test/passes/infer-types
parent2bd423fa061fb3e0973fa83e98f2877fd4616746 (diff)
Changed stanza output of UInt/SInt to include widths. Made tests match accordingly
Diffstat (limited to 'test/passes/infer-types')
-rw-r--r--test/passes/infer-types/bundle.fir2
-rw-r--r--test/passes/infer-types/gcd.fir2
2 files changed, 2 insertions, 2 deletions
diff --git a/test/passes/infer-types/bundle.fir b/test/passes/infer-types/bundle.fir
index 12cc58b1..0a2d2e4f 100644
--- a/test/passes/infer-types/bundle.fir
+++ b/test/passes/infer-types/bundle.fir
@@ -26,7 +26,7 @@ circuit top :
;CHECK: node y = z@<t:{ x : UInt, flip y : SInt}>.y@<t:SInt>
;CHECK: wire a : UInt<3>[10]@<t:UInt>@<t:UInt[10]@<t:UInt>>
;CHECK: node b = a@<t:UInt[10]@<t:UInt>>[2]@<t:UInt>
-;CHECK: node c = a@<t:UInt[10]@<t:UInt>>[UInt("h3")@<t:UInt>]
+;CHECK: node c = a@<t:UInt[10]@<t:UInt>>[UInt<2>("h3")@<t:UInt>]
;CHECK: Finished Infer Types
diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir
index d419ce35..398a4944 100644
--- a/test/passes/infer-types/gcd.fir
+++ b/test/passes/infer-types/gcd.fir
@@ -20,7 +20,7 @@ circuit top :
reg y : UInt,clk with :
reset => (reset,UInt(42))
; CHECK: reg x : UInt, clk@<t:Clock> with :
- ;CHECK:reset => (reset@<t:UInt>, UInt("h0")@<t:UInt>)
+ ;CHECK:reset => (reset@<t:UInt>, UInt<1>("h0")@<t:UInt>)
when gt(x, y) :
;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> :
inst s of subtracter