aboutsummaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Expand)Author
2016-12-05Add check for muxing between clocks (#360)Jack Koenig
2016-12-05Bugfix: expand whens not voiding memories (#380)Adam Izraelevitz
2016-11-30Bugfix: Dedup aggressively (ignore comments) (#375)Adam Izraelevitz
2016-11-23Stringified annotations (#367)Adam Izraelevitz
2016-11-21Bugfix: exponential runtime of pull muxes (#379)Adam Izraelevitz
2016-11-21Rewrote inline xform to fix quadratic perf. bug (#377)Adam Izraelevitz
2016-11-15Fixed multi wiring (#368)Adam Izraelevitz
2016-11-14Fix wrong omitting same clocked nondirect children (#374)Adam Izraelevitz
2016-11-10Added additional optimizationsazidar
2016-11-09Added optimizations to for better width inferenceazidar
2016-11-09Bugfix: removed recursive removal in infer widthsazidar
2016-11-07Clock List Transform (#365)Adam Izraelevitz
2016-11-07Fix annotations (#366)Adam Izraelevitz
2016-11-07make default dir be current directory (#361)Chick Markley
2016-11-07Added underscore to GEN, now its _GEN (#362)Adam Izraelevitz
2016-11-05Fix CHIRRTL bugs (#355)Donggyu
2016-11-04Cleanup license at top of every file (#364)Jack Koenig
2016-11-04Add a pass to deduplicate modulesazidar
2016-11-04Refactor Compilers and Transformsjackkoenig
2016-11-03Added Legalize to MiddleToLowFirrtlazidar
2016-11-01Fix Match Error in Check Types on Partial Connect (#359)Jack Koenig
2016-11-01fix bug. remove spurious connect that reassigns node (#358)Scott Beamer
2016-10-31Fixed Verilog emission of andr, orr, and xorr (#357)Adam Izraelevitz
2016-10-30Cleanup fixed point tests (#339)Jack Koenig
2016-10-30Keep package name + directory structure consistent (#354)Colin Schmidt
2016-10-27Wiring (#348)Adam Izraelevitz
2016-10-26Improve reference & name resolution in ReplSeqMem (#352)Donggyu
2016-10-26Add RawString ExtModule parameter supportjackkoenig
2016-10-26Add Support for Parameterized ExtModules and Name Overridejackkoenig
2016-10-26Add ExtModule Testsjackkoenig
2016-10-26Improve integration test API and add support for Verilog resourcesjackkoenig
2016-10-25Logger 1 (#338)Chick Markley
2016-10-24match fromBits order with toBits, toBitMask (#349)Donggyu
2016-10-23Fix bitmask (#346)Angie Wang
2016-10-20fix resolve memory reference (#341)Donggyu
2016-10-19annotations being assembled form command line but not being passed down to fi...chick
2016-10-18Create a simple system for executions and command line parameters (#337)Chick Markley
2016-10-17Reorganized memory blackboxing (#336)Adam Izraelevitz
2016-10-17Add fixed point type (#322)Adam Izraelevitz
2016-10-11Scala style cleanup take 5 (#324)Chick Markley
2016-10-07Add test for Firrtl mems with no ports (#327)Jack Koenig
2016-10-07change default info mode to append (#328)Colin Schmidt
2016-09-29Merge branch 'master' into fix_infer_mdirJim Lawson
2016-09-27eliminate postfix operator problematic statementschick
2016-09-27remove unnecessary parentheseschick
2016-09-27enclosing block redundantchick
2016-09-27No return type for implicit functionchick
2016-09-27Anonymous function convertible to a method valuechick
2016-09-26add CInferMDirSpecDonggyu Kim
2016-09-26fix CInferMDir on SubAccessDonggyu Kim