diff options
| author | chick | 2016-09-25 18:20:36 -0700 |
|---|---|---|
| committer | jackkoenig | 2016-09-27 13:06:52 -0700 |
| commit | 39f06c4cff41030e7802c7b371123e040d9c447b (patch) | |
| tree | 9b004b9ec12d0db0a417902e3a62b4f4d3ff2eab /src | |
| parent | 516339c30fd453ffa90dea6c0c255f84b0db567f (diff) | |
enclosing block redundant
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogMemDelays.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/VerilogMemDelays.scala index f6177606..325e4ba2 100644 --- a/src/main/scala/firrtl/passes/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/VerilogMemDelays.scala @@ -63,7 +63,7 @@ object VerilogMemDelays extends Pass { val ports = (s.readers ++ s.writers).toSet def newPortName(rw: String, p: String) = (for { idx <- Stream from 0 - newName = s"${rw}_${p}_${idx}" + newName = s"${rw}_${p}_$idx" if !ports(newName) } yield newName).head val rwMap = (s.readwriters map (rw => |