From 39f06c4cff41030e7802c7b371123e040d9c447b Mon Sep 17 00:00:00 2001
From: chick
Date: Sun, 25 Sep 2016 18:20:36 -0700
Subject: enclosing block redundant

---
 src/main/scala/firrtl/passes/VerilogMemDelays.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/passes/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/VerilogMemDelays.scala
index f6177606..325e4ba2 100644
--- a/src/main/scala/firrtl/passes/VerilogMemDelays.scala
+++ b/src/main/scala/firrtl/passes/VerilogMemDelays.scala
@@ -63,7 +63,7 @@ object VerilogMemDelays extends Pass {
       val ports = (s.readers ++ s.writers).toSet
       def newPortName(rw: String, p: String) = (for {
         idx <- Stream from 0
-        newName = s"${rw}_${p}_${idx}"
+        newName = s"${rw}_${p}_$idx"
         if !ports(newName)
       } yield newName).head
       val rwMap = (s.readwriters map (rw =>
-- 
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