diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/main/scala/firrtl/passes/VerilogMemDelays.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/passes/VerilogMemDelays.scala b/src/main/scala/firrtl/passes/VerilogMemDelays.scala index f6177606..325e4ba2 100644 --- a/src/main/scala/firrtl/passes/VerilogMemDelays.scala +++ b/src/main/scala/firrtl/passes/VerilogMemDelays.scala @@ -63,7 +63,7 @@ object VerilogMemDelays extends Pass { val ports = (s.readers ++ s.writers).toSet def newPortName(rw: String, p: String) = (for { idx <- Stream from 0 - newName = s"${rw}_${p}_${idx}" + newName = s"${rw}_${p}_$idx" if !ports(newName) } yield newName).head val rwMap = (s.readwriters map (rw => |