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2020-02-13Update ScalaTest deprecations. (#1382)Jim Lawson
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-13Constant prop binary PrimOps with matching argumentsAlbert Magyar
* Add SimplifyBinaryOp trait * Add extra functionality to comparison folding * Add tests * Fix comments from review
2020-02-13Add tests for (Un)?reachable InstanceGraph MethodsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Add test of RenameMap not recording same renameSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Add test of RenameMap self-renamingSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Repl seq mem renaming (#1286)Jack Koenig
* Consume NoDedupMemAnnotations in ResolveMemoryReference The ComponentName being pointed to by the annotation no longer exists after ReplaceSeqMems so we should consume the annotations * Support renaming in ReplaceMemMacros Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-11Add InstanceGraph.staticInstanceCount testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-12Removed unused imports in src/test/ (#1381)Jim Lawson
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-12Fixing lint error: x + -1 (#1374)Adam Izraelevitz
* Generates lint-clean Verilog for the case: x + -1 ...where x is anything and 1 is any literal. Master behavior: input x : SInt<8> output z : SInt<9> z <= add(x, SInt(-2)) generates assign z = $signed(x) + -8'sh2; After this PR: assign z = $signed(x) - 8'sh2; If the literal is the maximum possible literal, a special case is triggered to properly trim the resulting subtraction. Input: input x : SInt<2> output z : SInt<3> z <= add(x, SInt(-2)) now generates (after this PR) assign z = $signed(x) - 3'sh2; * Updated documentation * Change ArrayBuffer to ListBuffer * Change name to minNegValue * Remove mutable public interfaces Co-authored-by: Albert Magyar <albert.magyar@gmail.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-02-10Test EliminateTargetPaths ModuleTarget anno dupingSchuyler Eldridge
Add a test that EliminateTargetPaths properly duplicates an annotation pointing at a ModuleTarget. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-02-07Add extra 'de-optimization' opportunity for register const prop testAlbert Magyar
2020-02-06Better register const prop through speculative de-optimizationAlbert Magyar
* Fixes #1240 * Add failing reg const prop test case from #1240
2020-02-06Add constant prop to async regs (#1355)Adam Izraelevitz
* Add constant prop to async regs * Added another test of no reset value but constant assignment * Clarify name of updateNodeMap * Update constant assignment of async reset to not be inferred as a latch, works with donttouch * Revert "Update constant assignment of async reset to not be inferred as a latch, works with donttouch" This reverts commit 952bf38127cb32f814496a2b4b3bfb173d532728.
2020-02-06[Behavior change] Andr of zero-width wire now returns UIntLiteral(1)Albert Magyar
* Fixes #1344
2020-02-06Emit 'else' case for trivial-valued async reset regs to avoid latches (#1359)Albert Magyar
2020-01-15Verilog emitter transform InlineBitExtractions (#1296)John Ingalls
* transform InlineBitExtractions * InlineNotsTransform, InlineBitExtractionsTransform: inputForm/outputForm = UnknownForm * clean up some minor redundancies from Adam review * clarifications from Seldrige review
2020-01-15improve the tail ir usability. (#1241)Sequencer
Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-15Filter ResolvePaths in EliminateTargetPaths (#1310)Schuyler Eldridge
Change EliminateTargetPaths to remove ResolvePaths annotations in the output AnnotationSeq. This prevents a bug whereby the upstream ResolvePaths annotations from previous runs of EliminateTargetPaths can result in unexpected duplication. Adds a test that checks that ResolvePaths annotations are actually removed. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
2020-01-10Change LoggerState.globalLevel to Warn (#1307)Jim Lawson
* Change LoggerState.globalLevel to Warn PR #1305 changes the `globalLogLevel` in `LogLevelAnnotation` to from `None` to `Warn`. Update the default `LoggerState.globalLevel` to `Warn` as well. * Update LoggerSpec tests to match globalLogLevel of Warn * Add test of behavior for LogLevel.None
2020-01-09Dedup PassTests, add NoCircuitDedupAnnotations (#1302)Schuyler Eldridge
Change PassTests to include Dedup when running transforms. This makes PassTests behave more like an actual compiler. Fixes bugs in Inline, Flatten, and Grouping tests where the tests would only work without deduplication. This adds NoCircuiDedupAnnotations to prevent deduplication for the offending tests. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2020-01-07Remove printlns from testsJack Koenig
2020-01-07Switch compileFirrtlTest from Driver to FirrtlStageJack Koenig
2020-01-07Redirect testing shell commands to loggerJack Koenig
This includes the built-in functions in BackendCompilationUtilities which are a public API
2020-01-07Fix literals cast to Clocks in Print and StopJack Koenig
Many tools don't except 'always @(posedge 1'h0)' so we assign the literal to a wire and use that as the posedge target.
2020-01-07Remove unnecessary $signed casts for PrimOps in Verilog EmitterJack Koenig
[skip formal checks] Adds new InlineCastsTransform to the VerilogEmitter which removes Statements that do nothing but cast by inlining the cast Expression
2020-01-07Remove unnecessary casts in Constant PropagationJack Koenig
2020-01-06Verilog emitter transform InlineNots (#1270)John Ingalls
[skip formal checks] * ConstProp FoldEqual/FoldNotEqual propagate boolean (non-)equality with true/false * transform InlineNots * transform back-to-back Nots into straight rename * swap mux with inverted select Co-authored-by: Jack Koenig <jack.koenig3@gmail.com>
2019-12-30Respect last connect semantics in InferResetsJack Koenig
InferResets will now support last connect semantics (within the same scope) when determining the concrete reset type for components of type Reset. This only includes *unconditional* last connects; it remains illegal to drive a component of type Reset with different concrete types under differing when conditions. For example, the following is now legal: input a : UInt<1> input b : AsyncReset output z : Reset z <= a z <= b The second connect will when and z will be of type AsyncReset. The following remains illegal: input a : UInt<1> input b : AsyncReset input c : UInt<1> output z : Reset z <= a when c : z <= b This commit also ensures that components of type Reset with no drivers (or only invalidation) default to type UInt<1>. This fixes a bug where the transform would crash with such input.
2019-11-29Remove scala-logging fully in favor of our own loggerJack Koenig
There was some vestigial logging that conflicts with the homebrewed logger used by most of the codebase
2019-11-19Error when blackboxing memories with unsupported masking (#1238)Abraham Gonzalez
* Types containing bundles can't generally be converted to a single mask granularity * Update ReplSeqMemTests to check for illegal masks
2019-11-14Add test with Transform inside objectSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-11-07Add check for multiple sources for same wiring pin (#1191)Jack Koenig
2019-11-05Move CheckResets after CheckCombLoops (#1224)Jack Koenig
Recursive literal lookup needs to be guarded against combinational loops Added a test-case to illustrate the issue when CheckResets is run before CheckCombLoops
2019-11-04Merge branch 'master' into serialization-utilsJack Koenig
2019-11-04Ignore extmodule instances in Flatten (#1218)Albert Magyar
* Closes #1162 * Instances of extmodules remain in the final hierarchy * Extmodule definitions are not renamed or duplicated * The rest of the pass may proceed as normal
2019-11-04Add explicit EOF to top-level parser rule (#1217)Albert Magyar
* Fixes #1154 * Tests that #1154 example produces SyntaxErrorsException * Generally helps catch trailing syntax errors * Performance-neutral relative to previous grammar * Recommended by antlr4 devs, can help performance in some cases * See antlr/antlr4#1540
2019-10-31Guard initial blocks in emitted Verilog with `ifndef SYNTHESISJack Koenig
2019-10-30Add some simple tests to demonstrate how to provide type hintsDavid Biancolin
2019-10-29Change findInstancesInHierarchy to return implicit top instanceAlbert Magyar
* Change FIRRTL-internal API, affecting only one corner case * Make API more "DWIM" and consistent with other methods * Add test cases for findInstancesInHierarchy * Update Scaladoc
2019-10-22Add Register Updates/else-if Verilog Emitter testsSchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-10-21Add tests for memories with latency >1, toggling enablesAlbert Magyar
2019-10-21Add library for streamlined Verilog execution testsAlbert Magyar
2019-10-21Add test for #1179: comb-loops from VerilogMemDelaysAlbert Magyar
2019-10-18Upstream intervals (#870)Adam Izraelevitz
Major features: - Added Interval type, as well as PrimOps asInterval, clip, wrap, and sqz. - Changed PrimOp names: bpset -> setp, bpshl -> incp, bpshr -> decp - Refactored width/bound inferencer into a separate constraint solver - Added transforms to infer, trim, and remove interval bounds - Tests for said features Plan to be released with 1.3
2019-10-08Add test for TopWiringTransform idempotencySchuyler Eldridge
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-30Implement read-first memories in VerilogMemDelaysAlbert Magyar
* Corrects behavior under write collisions * Avoids heavily refactoring pass
2019-09-30Improve read-under-write parameter supportAlbert Magyar
* Make the read-under-write (RUW) parameter typesafe * Add RUW support to the FIRRTL proto and CHIRRTL grammar
2019-09-19Faster inline renaming (#1184)Albert Chen
* dont chain inline and refix RenameMaps * cache already inlined modules * reduce number of chained RenameMaps * InlineInstances: cleanup and add comments
2019-09-16Rename gender to flowSchuyler Eldridge
The following names are changed: - gender -> flow - Gender -> Flow - MALE -> SourceFlow - FEMALE -> SinkFlow - BIGENDER -> DuplexFlow - UNKNOWNGENDER -> UnknownFlow Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
2019-09-12update inline transform and testcasesAbert Chen
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