Rename gender to flow

The following names are changed:
  - gender        -> flow
  - Gender        -> Flow
  - MALE          -> SourceFlow
  - FEMALE        -> SinkFlow
  - BIGENDER      -> DuplexFlow
  - UNKNOWNGENDER -> UnknownFlow

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>

15 files changed, 76 insertions, 79 deletions

diff --git a/src/test/scala/firrtlTests/CheckInitializationSpec.scala b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
index 9b1f3a9c..3af63c6e 100644
--- a/src/test/scala/firrtlTests/CheckInitializationSpec.scala
+++ b/src/test/scala/firrtlTests/CheckInitializationSpec.scala
@@ -16,8 +16,8 @@ class CheckInitializationSpec extends FirrtlFlatSpec {
      ResolveKinds,
      InferTypes,
      CheckTypes,
-     ResolveGenders,
-     CheckGenders,
+     ResolveFlows,
+     CheckFlows,
      new InferWidths,
      CheckWidths,
      PullMuxes,
diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 54dc60ab..96275003 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -5,7 +5,7 @@ package firrtlTests
 import org.scalatest._
 import firrtl.{Parser, CircuitState, UnknownForm, Transform}
 import firrtl.ir.Circuit
-import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassException,InferWidths,CheckWidths,ResolveGenders,CheckGenders}
+import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassException,InferWidths,CheckWidths,ResolveFlows,CheckFlows}
 
 class CheckSpec extends FlatSpec with Matchers {
   val defaultPasses = Seq(ToWorkingIR, CheckHighForm)
@@ -176,8 +176,8 @@ class CheckSpec extends FlatSpec with Matchers {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths)
     val input =
diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index aeb70c8d..fba81ec7 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -16,8 +16,8 @@ class ChirrtlSpec extends FirrtlFlatSpec {
     ResolveKinds,
     InferTypes,
     CheckTypes,
-    ResolveGenders,
-    CheckGenders,
+    ResolveFlows,
+    CheckFlows,
     new InferWidths,
     CheckWidths,
     PullMuxes,
diff --git a/src/test/scala/firrtlTests/ClockListTests.scala b/src/test/scala/firrtlTests/ClockListTests.scala
index dde719d5..a30416b3 100644
--- a/src/test/scala/firrtlTests/ClockListTests.scala
+++ b/src/test/scala/firrtlTests/ClockListTests.scala
@@ -24,7 +24,7 @@ class ClockListTests extends FirrtlFlatSpec {
     ToWorkingIR,
     ResolveKinds,
     InferTypes,
-    ResolveGenders,
+    ResolveFlows,
     new InferWidths
   )
 
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index da3e9b41..79e73c80 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -13,7 +13,7 @@ class ConstantPropagationSpec extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       new ConstantPropagation)
   protected def exec(input: String) = {
diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
index a1ac8a31..af82cc38 100644
--- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala
+++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
@@ -20,8 +20,8 @@ class ExpandWhensSpec extends FirrtlFlatSpec {
     Uniquify,
     ResolveKinds,
     InferTypes,
-    ResolveGenders,
-    CheckGenders,
+    ResolveFlows,
+    CheckFlows,
     new InferWidths,
     CheckWidths,
     PullMuxes,
@@ -141,4 +141,3 @@ class ExpandWhensSpec extends FirrtlFlatSpec {
 }
 
 class ExpandWhensExecutionTest extends ExecutionTest("ExpandWhens", "/passes/ExpandWhens")
-
diff --git a/src/test/scala/firrtlTests/LowerTypesSpec.scala b/src/test/scala/firrtlTests/LowerTypesSpec.scala
index 30ef795b..be9d738b 100644
--- a/src/test/scala/firrtlTests/LowerTypesSpec.scala
+++ b/src/test/scala/firrtlTests/LowerTypesSpec.scala
@@ -18,8 +18,8 @@ class LowerTypesSpec extends FirrtlFlatSpec {
     ResolveKinds,
     InferTypes,
     CheckTypes,
-    ResolveGenders,
-    CheckGenders,
+    ResolveFlows,
+    CheckFlows,
     new InferWidths,
     CheckWidths,
     PullMuxes,
@@ -31,7 +31,7 @@ class LowerTypesSpec extends FirrtlFlatSpec {
     new ConstantPropagation,
     ResolveKinds,
     InferTypes,
-    ResolveGenders,
+    ResolveFlows,
     new InferWidths,
     LowerTypes)
 
diff --git a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala
index 64977c7f..e9ef3bcd 100644
--- a/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala
+++ b/src/test/scala/firrtlTests/ReplaceAccessesSpec.scala
@@ -13,7 +13,7 @@ class ReplaceAccessesSpec extends FirrtlFlatSpec {
     ToWorkingIR,
     ResolveKinds,
     InferTypes,
-    ResolveGenders,
+    ResolveFlows,
     new InferWidths,
     ReplaceAccesses)
   protected def exec(input: String) = {
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 0ef4f709..b7df945f 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -95,7 +95,7 @@ class UnitTests extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       ExpandConnects)
     val input =
      """circuit Unit :
@@ -157,7 +157,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       SplitExpressions
     )
@@ -181,7 +181,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       PadWidths
     )
@@ -202,7 +202,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       PullMuxes,
       ExpandConnects,
@@ -210,8 +210,8 @@ class UnitTests extends FirrtlFlatSpec {
       new ConstantPropagation
     )
     val input =
-      """circuit AssignViaDeref : 
-         |  module AssignViaDeref : 
+      """circuit AssignViaDeref :
+         |  module AssignViaDeref :
          |    input clock : Clock
          |    input reset : UInt<1>
          |    output io : {a : UInt<8>, sel : UInt<1>}
@@ -242,7 +242,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -261,7 +261,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -280,7 +280,7 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -388,12 +388,12 @@ class UnitTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       PullMuxes,
       ExpandConnects,
       RemoveAccesses,
-      ResolveGenders,
+      ResolveFlows,
       new ConstantPropagation
     )
     val input =
@@ -412,13 +412,13 @@ class UnitTests extends FirrtlFlatSpec {
     val ut2 = UIntType(IntWidth(BigInt(2)))
     val ut1 = UIntType(IntWidth(BigInt(1)))
 
-    val mgen = WRef("_array_index", ut16, WireKind, MALE)
-    val fgen = WRef("_array_index", ut16, WireKind, FEMALE)
-    val index = WRef("index", ut2, PortKind, MALE)
-    val out = WRef("out", ut16, PortKind, FEMALE)
+    val mgen = WRef("_array_index", ut16, WireKind, SourceFlow)
+    val fgen = WRef("_array_index", ut16, WireKind, SinkFlow)
+    val index = WRef("index", ut2, PortKind, SourceFlow)
+    val out = WRef("out", ut16, PortKind, SinkFlow)
 
     def eq(e1: Expression, e2: Expression): Expression = DoPrim(PrimOps.Eq, Seq(e1, e2), Nil, ut1)
-    def array(v: Int): Expression = WSubIndex(WRef("array", VectorType(ut16, 3), WireKind, MALE), v, ut16, MALE)
+    def array(v: Int): Expression = WSubIndex(WRef("array", VectorType(ut16, 3), WireKind, SourceFlow), v, ut16, SourceFlow)
 
     result should containTree { case DefWire(_, "_array_index", `ut16`) => true }
     result should containTree { case IsInvalid(_, `fgen`) => true }
diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 96bd249c..4c0e7f70 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -53,7 +53,7 @@ class WidthSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -76,7 +76,7 @@ class WidthSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -95,7 +95,7 @@ class WidthSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -120,7 +120,7 @@ class WidthSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths)
     val input =
       """circuit Unit :
@@ -142,7 +142,7 @@ class WidthSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths)
     val input =
       """circuit Unit :
@@ -165,7 +165,7 @@ class WidthSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
     val input =
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala
index 4fe4a46c..ec69c39f 100644
--- a/src/test/scala/firrtlTests/WiringTests.scala
+++ b/src/test/scala/firrtlTests/WiringTests.scala
@@ -33,7 +33,7 @@ class WiringTests extends FirrtlFlatSpec {
     ToWorkingIR,
     ResolveKinds,
     InferTypes,
-    ResolveGenders,
+    ResolveFlows,
     new InferWidths
   )
 
diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala
index eb955f29..eb3d1a96 100644
--- a/src/test/scala/firrtlTests/ZeroWidthTests.scala
+++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala
@@ -15,7 +15,7 @@ class ZeroWidthTests extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       ZeroWidth)
   private def exec (input: String) = {
@@ -218,12 +218,12 @@ class ZeroWidthVerilog extends FirrtlFlatSpec {
   "Circuit" should "accept zero width wires" in {
     val compiler = new VerilogCompiler
     val input =
-      """circuit Top : 
-         |  module Top : 
+      """circuit Top :
+         |  module Top :
          |    input y: UInt<0>
          |    output x: UInt<3>
          |    x <= y""".stripMargin
-    val check = 
+    val check =
       """module Top(
         |  output  [2:0] x
         |);
diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
index 667db7b0..6bf86479 100644
--- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
@@ -28,8 +28,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -58,8 +58,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -84,8 +84,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -110,8 +110,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -136,8 +136,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -162,8 +162,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -188,8 +188,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -228,8 +228,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths)
     val input =
@@ -254,8 +254,8 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths,
       ConvertFixedToSInt)
@@ -334,4 +334,3 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
     executeTest(input("cmem"), check(0, 1, 1).split("\n") map normalized, new LowFirrtlCompiler)
   }
 }
-
diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
index 21a39e83..8686bd0f 100644
--- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
@@ -28,8 +28,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths,
       ConvertFixedToSInt)
@@ -58,8 +58,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths,
       ConvertFixedToSInt)
@@ -89,8 +89,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths,
       ConvertFixedToSInt)
@@ -116,8 +116,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths,
       ConvertFixedToSInt)
@@ -143,8 +143,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths,
       ConvertFixedToSInt)
@@ -195,8 +195,8 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
-      CheckGenders,
+      ResolveFlows,
+      CheckFlows,
       new InferWidths,
       CheckWidths,
       ConvertFixedToSInt)
@@ -215,4 +215,3 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
     executeTest(input, check.split("\n") map normalized, passes)
   }
 }
-
diff --git a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
index 54a3df40..46fb310a 100644
--- a/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/InferWidthsWithAnnosSpec.scala
@@ -35,7 +35,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
 
@@ -64,7 +64,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
 
@@ -107,7 +107,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec {
       ResolveKinds,
       InferTypes,
       CheckTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths)
 
@@ -156,7 +156,7 @@ class InferWidthsWithAnnosSpec extends FirrtlFlatSpec {
       ToWorkingIR,
       ResolveKinds,
       InferTypes,
-      ResolveGenders,
+      ResolveFlows,
       new InferWidths,
       CheckWidths,
       new WiringTransform,