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authorAlbert Magyar2019-11-04 13:12:59 -0800
committermergify[bot]2019-11-04 21:12:59 +0000
commit0d7defc81b02c41e416237ad226adc5f1ab0f8f2 (patch)
treebc9ba3e5b4bc145ff2857431fbd27ae47ae64539 /src/test
parent8f108c1aa8cac656da56b2505519db47080d5a26 (diff)
Ignore extmodule instances in Flatten (#1218)
* Closes #1162 * Instances of extmodules remain in the final hierarchy * Extmodule definitions are not renamed or duplicated * The rest of the pass may proceed as normal
Diffstat (limited to 'src/test')
-rw-r--r--src/test/scala/firrtlTests/FlattenTests.scala78
1 files changed, 62 insertions, 16 deletions
diff --git a/src/test/scala/firrtlTests/FlattenTests.scala b/src/test/scala/firrtlTests/FlattenTests.scala
index 82c3ebdc..468cc1c4 100644
--- a/src/test/scala/firrtlTests/FlattenTests.scala
+++ b/src/test/scala/firrtlTests/FlattenTests.scala
@@ -25,7 +25,7 @@ class FlattenTests extends LowTransformSpec {
val name = if (parts.size == 1) modName else ComponentName(parts.tail.mkString("."), modName)
FlattenAnnotation(name)
}
-
+
"The modules inside Top " should "be inlined" in {
val input =
"""circuit Top :
@@ -55,7 +55,7 @@ class FlattenTests extends LowTransformSpec {
| b <= a""".stripMargin
execute(input, check, Seq(flatten("Top")))
}
-
+
"Two instances of the same module inside Top " should "be inlined" in {
val input =
"""circuit Top :
@@ -112,14 +112,14 @@ class FlattenTests extends LowTransformSpec {
| input a : UInt<32>
| output b : UInt<32>
| inst i of Inline2
- | i.a <= a
- | b <= i.a
+ | i.a <= a
+ | b <= i.a
| module Inline1 :
| input a : UInt<32>
| output b : UInt<32>
| inst i of Inline2
- | i.a <= a
- | b <= i.a
+ | i.a <= a
+ | b <= i.a
| module Inline2 :
| input a : UInt<32>
| output b : UInt<32>
@@ -147,13 +147,13 @@ class FlattenTests extends LowTransformSpec {
| input a : UInt<32>
| output b : UInt<32>
| inst i of Inline2
- | b <= i.a
- | i.a <= a
+ | b <= i.a
+ | i.a <= a
| module Inline1 :
| input a : UInt<32>
| output b : UInt<32>
- | inst i of Inline2
- | b <= i.a
+ | inst i of Inline2
+ | b <= i.a
| i.a <= a
| module Inline2 :
| input a : UInt<32>
@@ -179,14 +179,14 @@ class FlattenTests extends LowTransformSpec {
| input a : UInt<32>
| output b : UInt<32>
| inst i of Inline2
- | i.a <= a
- | b <= i.a
+ | i.a <= a
+ | b <= i.a
| module Inline1 :
| input a : UInt<32>
| output b : UInt<32>
| inst i of Inline2
- | i.a <= a
- | b <= i.a
+ | i.a <= a
+ | b <= i.a
| module Inline2 :
| input a : UInt<32>
| output b : UInt<32>
@@ -208,8 +208,8 @@ class FlattenTests extends LowTransformSpec {
| input a : UInt<32>
| output b : UInt<32>
| inst i of Inline2
- | b <= i.a
- | i.a <= a
+ | b <= i.a
+ | i.a <= a
| module Inline1 :
| input a : UInt<32>
| output b : UInt<32>
@@ -234,4 +234,50 @@ class FlattenTests extends LowTransformSpec {
|""".stripMargin
execute(input, input, Seq.empty)
}
+
+ "The Flatten transform" should "ignore extmodules" in {
+ val input = """
+ |circuit Top :
+ | module Top :
+ | input a : UInt<32>
+ | output b : UInt<32>
+ | inst i of Inline
+ | i.a <= a
+ | b <= i.b
+ | module Inline :
+ | input a : UInt<32>
+ | output b : UInt<32>
+ | inst i of ExternalMod
+ | i.a <= a
+ | b <= i.b
+ | extmodule ExternalMod :
+ | input a : UInt<32>
+ | output b : UInt<32>
+ | defname = ExternalMod
+ """.stripMargin
+ val check = """
+ |circuit Top :
+ | module Top :
+ | input a : UInt<32>
+ | output b : UInt<32>
+ | wire i_a : UInt<32>
+ | wire i_b : UInt<32>
+ | inst i_i of ExternalMod
+ | i_b <= i_i.b
+ | i_i.a <= i_a
+ | b <= i_b
+ | i_a <= a
+ | module Inline :
+ | input a : UInt<32>
+ | output b : UInt<32>
+ | inst i of ExternalMod
+ | b <= i.b
+ | i.a <= a
+ | extmodule ExternalMod :
+ | input a : UInt<32>
+ | output b : UInt<32>
+ | defname = ExternalMod
+ """.stripMargin
+ execute(input, check, Seq(flatten("Top")))
+ }
}