Remove printlns from tests

4 files changed, 5 insertions, 9 deletions

diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index e0ed6fdb..42ba031a 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -79,7 +79,7 @@ class CustomTransformSpec extends FirrtlFlatSpec {
       def inputForm = HighForm
       def outputForm = HighForm
       def execute(s: CircuitState) = {
-        println(name)
+        assert(name.endsWith("A"))
         s
       }
     }
diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala
index 88a39a01..4df711b3 100644
--- a/src/test/scala/firrtlTests/DriverSpec.scala
+++ b/src/test/scala/firrtlTests/DriverSpec.scala
@@ -76,21 +76,21 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities
       val optionsManager = new ExecutionOptionsManager("test")
 
       optionsManager.parse(Array("--top-name", "dog", "fox", "tardigrade", "stomatopod")) should be(true)
-      println(s"programArgs ${optionsManager.commonOptions.programArgs}")
+      info(s"programArgs ${optionsManager.commonOptions.programArgs}")
       optionsManager.commonOptions.programArgs.length should be(3)
       optionsManager.commonOptions.programArgs should be("fox" :: "tardigrade" :: "stomatopod" :: Nil)
 
       optionsManager.commonOptions = CommonOptions()
       optionsManager.parse(
         Array("dog", "stomatopod")) should be(true)
-      println(s"programArgs ${optionsManager.commonOptions.programArgs}")
+      info(s"programArgs ${optionsManager.commonOptions.programArgs}")
       optionsManager.commonOptions.programArgs.length should be(2)
       optionsManager.commonOptions.programArgs should be("dog" :: "stomatopod" :: Nil)
 
       optionsManager.commonOptions = CommonOptions()
       optionsManager.parse(
         Array("fox", "--top-name", "dog", "tardigrade", "stomatopod")) should be(true)
-      println(s"programArgs ${optionsManager.commonOptions.programArgs}")
+      info(s"programArgs ${optionsManager.commonOptions.programArgs}")
       optionsManager.commonOptions.programArgs.length should be(3)
       optionsManager.commonOptions.programArgs should be("fox" :: "tardigrade" :: "stomatopod" :: Nil)
 
@@ -504,7 +504,6 @@ class VcdSuppressionSpec extends FirrtlFlatSpec {
       assert(executeExpectingSuccess(prefix, testDir))
 
       val vcdFile = new File(s"$testDir/dump.vcd")
-      println(s"file ${vcdFile.getAbsolutePath} ${vcdFile.exists()}")
       vcdFile.exists() should be(! suppress)
     }
 
diff --git a/src/test/scala/firrtlTests/RenameMapSpec.scala b/src/test/scala/firrtlTests/RenameMapSpec.scala
index 3241db16..2da10b7f 100644
--- a/src/test/scala/firrtlTests/RenameMapSpec.scala
+++ b/src/test/scala/firrtlTests/RenameMapSpec.scala
@@ -161,7 +161,6 @@ class RenameMapSpec extends FirrtlFlatSpec {
         t.instOf("a", "A" + idx)
       }.ref("ref")
       val (millis, rename) = firrtl.Utils.time(renames.get(deepTarget))
-      println(s"${(deepTarget.tokens.size - 1) / 2} -> $millis")
       //rename should be(None)
     }
   }
@@ -281,7 +280,7 @@ class RenameMapSpec extends FirrtlFlatSpec {
     renames.record(top.module("E").instOf("f", "F"), top.module("E").ref("g"))
 
     a [IllegalRenameException] shouldBe thrownBy {
-      println(renames.get(top.module("E").instOf("f", "F").ref("g")))
+      renames.get(top.module("E").instOf("f", "F").ref("g"))
     }
   }
 
diff --git a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
index da154b6a..1bc4c927 100644
--- a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
@@ -9,7 +9,6 @@ import firrtlTests.FirrtlPropSpec
 class TargetSpec extends FirrtlPropSpec {
   def check(comp: Target): Unit = {
     val named = Target.convertTarget2Named(comp)
-    println(named)
     val comp2 = Target.convertNamed2Target(named)
     assert(comp.toGenericTarget.complete == comp2)
   }
@@ -43,7 +42,6 @@ class TargetSpec extends FirrtlPropSpec {
     val x_reg0_data = top.instOf("x", "X").ref("reg0").field("data")
     top.instOf("x", "x")
     top.ref("y")
-    println(x_reg0_data)
   }
   property("Should serialize and deserialize") {
     val circuit = CircuitTarget("Circuit")