diff options
| author | Albert Magyar | 2019-09-11 18:16:20 -0700 |
|---|---|---|
| committer | Albert Magyar | 2019-09-30 16:22:01 -0700 |
| commit | a10084fbba0ba88a1f0517b826ef8de44d8760d1 (patch) | |
| tree | 8a1ac0098409dbb95a45d3b7107a4f6d59d8e166 /src/test | |
| parent | 4ca2b859473e0a88723463eac2821cfbd3249c43 (diff) | |
Improve read-under-write parameter support
* Make the read-under-write (RUW) parameter typesafe
* Add RUW support to the FIRRTL proto and CHIRRTL grammar
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/ProtoBufSpec.scala | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/ProtoBufSpec.scala b/src/test/scala/firrtlTests/ProtoBufSpec.scala index 2f347c6d..7f41fb26 100644 --- a/src/test/scala/firrtlTests/ProtoBufSpec.scala +++ b/src/test/scala/firrtlTests/ProtoBufSpec.scala @@ -176,6 +176,21 @@ class ProtoBufSpec extends FirrtlFlatSpec { oldCMem should equal (cmem) } + // readunderwrite support + it should "support readunderwrite parameters" in { + val m1 = DefMemory(NoInfo, "m", UIntType(IntWidth(8)), 128, 1, 1, List("r"), List("w"), Nil, ir.ReadUnderWrite.Old) + FromProto.convert(ToProto.convert(m1).head.build) should equal (m1) + + val m2 = m1.copy(readUnderWrite = ir.ReadUnderWrite.New) + FromProto.convert(ToProto.convert(m2).head.build) should equal (m2) + + val cm1 = CDefMemory(NoInfo, "m", UIntType(IntWidth(8)), 128, true, ir.ReadUnderWrite.Old) + FromProto.convert(ToProto.convert(cm1).head.build) should equal (cm1) + + val cm2 = cm1.copy(readUnderWrite = ir.ReadUnderWrite.New) + FromProto.convert(ToProto.convert(cm2).head.build) should equal (cm2) + } + it should "support AsyncResetTypes" in { val port = ir.Port(ir.NoInfo, "reset", ir.Input, ir.AsyncResetType) FromProto.convert(ToProto.convert(port).build) should equal (port) |