Fixing lint error: x + -1 (#1374)

* Generates lint-clean Verilog for the case: x + -1

...where x is anything and 1 is any literal.

Master behavior:

  input x : SInt<8>
  output z : SInt<9>
  z <= add(x, SInt(-2))

generates

  assign z = $signed(x) + -8'sh2;

After this PR:

  assign z = $signed(x) - 8'sh2;

If the literal is the maximum possible literal, a special case is triggered to properly trim the resulting subtraction.

Input:

  input x : SInt<2>
  output z : SInt<3>
  z <= add(x, SInt(-2))

now generates (after this PR)

  assign z = $signed(x) - 3'sh2;

* Updated documentation

* Change ArrayBuffer to ListBuffer

* Change name to minNegValue

* Remove mutable public interfaces

Co-authored-by: Albert Magyar <albert.magyar@gmail.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

1 files changed, 37 insertions, 1 deletions

diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index bce9b155..f7f3a0bb 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -643,7 +643,7 @@ class VerilogEmitterSpec extends FirrtlFlatSpec {
         |z <= add(x, SInt(-1))
         |""".stripMargin
     )
-    result should containLine("assign z = $signed(x) + -4'sh1;")
+    result should containLine("assign z = $signed(x) - 4'sh1;")
   }
 
   it should "inline asSInt casts" in {
@@ -711,6 +711,42 @@ class VerilogEmitterSpec extends FirrtlFlatSpec {
     result should containLine("assign z = x == y;")
   }
 
+  it should "subtract positive literals instead of adding negative literals" in {
+    val compiler = new VerilogCompiler
+    val result = compileBody(
+      """input x : SInt<8>
+        |output z : SInt<9>
+        |z <= add(x, SInt(-2))
+        |""".stripMargin
+    )
+    result shouldNot containLine("assign z = $signed(x) + -8'sh2;")
+    result should    containLine("assign z = $signed(x) - 8'sh2;")
+  }
+
+  it should "subtract positive literals even with max negative literal" in {
+    val compiler = new VerilogCompiler
+    val result = compileBody(
+      """input x : SInt<2>
+        |output z : SInt<3>
+        |z <= add(x, SInt(-2))
+        |""".stripMargin
+    )
+    result shouldNot containLine("assign z = $signed(x) + -2'sh2;")
+    result should    containLine("assign z = $signed(x) - 3'sh2;")
+  }
+
+  it should "subtract positive literals even with max negative literal with no carryout" in {
+    val compiler = new VerilogCompiler
+    val result = compileBody(
+      """input x : SInt<2>
+        |output z : SInt<2>
+        |z <= add(x, SInt(-2))
+        |""".stripMargin
+    )
+    result shouldNot containLine("assign z = $signed(x) + -2'sh2;")
+    result should    containLine("assign _GEN_0 = $signed(x) - 3'sh2;")
+    result should    containLine("assign z = _GEN_0[1:0];")
+  }
 }
 
 class VerilogDescriptionEmitterSpec extends FirrtlFlatSpec {