improve the tail ir usability. (#1241)

Co-authored-by: Jim Lawson <ucbjrl@berkeley.edu>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>

1 files changed, 44 insertions, 0 deletions

diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index b7df945f..d2e2f295 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -20,6 +20,10 @@ class UnitTests extends FirrtlFlatSpec {
     }
   }
 
+  private def executeTest(input: String, expected: String, transforms: Seq[Transform]) = {
+    execute(input, transforms).circuit should be (parse(expected))
+  }
+
   def execute(input: String, transforms: Seq[Transform]): CircuitState = {
     val c = transforms.foldLeft(CircuitState(parse(input), UnknownForm)) {
       (c: CircuitState, t: Transform) => t.runTransform(c)
@@ -275,6 +279,26 @@ class UnitTests extends FirrtlFlatSpec {
     }
   }
 
+  "zero head select" should "return an empty module" in {
+    val passes = Seq(
+      ToWorkingIR,
+      ResolveKinds,
+      InferTypes,
+      ResolveFlows,
+      new InferWidths,
+      CheckWidths,
+      new DeadCodeElimination)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    node x = head(UInt(1), 0)""".stripMargin
+    val check =
+      """circuit Unit :
+        |  module Unit :
+        |    skip""".stripMargin
+    executeTest(input, check, passes)
+  }
+
   "Oversized tail select" should "throw an exception" in {
     val passes = Seq(
       ToWorkingIR,
@@ -294,6 +318,26 @@ class UnitTests extends FirrtlFlatSpec {
     }
   }
 
+  "max tail select" should "return an empty module" in {
+    val passes = Seq(
+      ToWorkingIR,
+      ResolveKinds,
+      InferTypes,
+      ResolveFlows,
+      new InferWidths,
+      CheckWidths,
+      new DeadCodeElimination)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    node x = tail(UInt(1), 1)""".stripMargin
+    val check =
+      """circuit Unit :
+        |  module Unit :
+        |    skip""".stripMargin
+    executeTest(input, check, passes)
+  }
+
   "Partial connecting incompatable types" should "throw an exception" in {
     val passes = Seq(
       ToWorkingIR,