diff options
| author | Albert Chen | 2019-09-19 14:55:15 -0700 |
|---|---|---|
| committer | Albert Magyar | 2019-09-19 14:55:14 -0700 |
| commit | 5e9b286185e98c58e5fde1987c48d085ebdb1e25 (patch) | |
| tree | 41b292cf71686186442cbffab03396a84a2adfb2 /src/test | |
| parent | 932b5d1ea66d3cc2475a22d21c237b0ed2ee9c09 (diff) | |
Faster inline renaming (#1184)
* dont chain inline and refix RenameMaps
* cache already inlined modules
* reduce number of chained RenameMaps
* InlineInstances: cleanup and add comments
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/InlineInstancesTests.scala | 85 | ||||
| -rw-r--r-- | src/test/scala/firrtlTests/PassTests.scala | 8 |
2 files changed, 93 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/InlineInstancesTests.scala b/src/test/scala/firrtlTests/InlineInstancesTests.scala index 5f48c883..36469064 100644 --- a/src/test/scala/firrtlTests/InlineInstancesTests.scala +++ b/src/test/scala/firrtlTests/InlineInstancesTests.scala @@ -459,6 +459,91 @@ class InlineInstancesTests extends LowTransformSpec { ) ) } + + "inlining both grandparent and grandchild" should "should work" in { + val input = + """circuit Top : + | module Top : + | input a : UInt<32> + | output b : UInt<32> + | inst i of Inline + | i.a <= a + | b <= i.b + | module Inline : + | input a : UInt<32> + | output b : UInt<32> + | inst foo of NestedInline + | inst bar of NestedNoInline + | foo.a <= a + | bar.a <= foo.b + | b <= bar.b + | module NestedInline : + | input a : UInt<32> + | output b : UInt<32> + | b <= a + | module NestedNoInline : + | input a : UInt<32> + | output b : UInt<32> + | inst foo of NestedInline + | foo.a <= a + | b <= foo.b + |""".stripMargin + val check = + """circuit Top : + | module Top : + | input a : UInt<32> + | output b : UInt<32> + | wire i_a : UInt<32> + | wire i_b : UInt<32> + | wire i_foo_a : UInt<32> + | wire i_foo_b : UInt<32> + | i_foo_b <= i_foo_a + | inst i_bar of NestedNoInline + | i_b <= i_bar.b + | i_foo_a <= i_a + | i_bar.a <= i_foo_b + | b <= i_b + | i_a <= a + | module NestedNoInline : + | input a : UInt<32> + | output b : UInt<32> + | wire foo_a : UInt<32> + | wire foo_b : UInt<32> + | foo_b <= foo_a + | b <= foo_b + | foo_a <= a + |""".stripMargin + val top = CircuitTarget("Top").module("Top") + val inlined = top.instOf("i", "Inline") + val nestedInlined = inlined.instOf("foo", "NestedInline") + val nestedNotInlined = inlined.instOf("bar", "NestedNoInline") + val innerNestedInlined = nestedNotInlined.instOf("foo", "NestedInline") + + executeWithAnnos(input, check, + Seq( + inline("Inline"), + inline("NestedInline"), + DummyAnno(inlined.ref("a")), + DummyAnno(inlined.ref("b")), + DummyAnno(nestedInlined.ref("a")), + DummyAnno(nestedInlined.ref("b")), + DummyAnno(nestedNotInlined.ref("a")), + DummyAnno(nestedNotInlined.ref("b")), + DummyAnno(innerNestedInlined.ref("a")), + DummyAnno(innerNestedInlined.ref("b")) + ), + Seq( + DummyAnno(top.ref("i_a")), + DummyAnno(top.ref("i_b")), + DummyAnno(top.ref("i_foo_a")), + DummyAnno(top.ref("i_foo_b")), + DummyAnno(top.instOf("i_bar", "NestedNoInline").ref("a")), + DummyAnno(top.instOf("i_bar", "NestedNoInline").ref("b")), + DummyAnno(top.instOf("i_bar", "NestedNoInline").ref("foo_a")), + DummyAnno(top.instOf("i_bar", "NestedNoInline").ref("foo_b")) + ) + ) + } } // Execution driven tests for inlining modules diff --git a/src/test/scala/firrtlTests/PassTests.scala b/src/test/scala/firrtlTests/PassTests.scala index 7fe154ec..6e12dd5b 100644 --- a/src/test/scala/firrtlTests/PassTests.scala +++ b/src/test/scala/firrtlTests/PassTests.scala @@ -38,6 +38,14 @@ abstract class SimpleTransformSpec extends FlatSpec with FirrtlMatchers with Com logger.debug(actual) logger.debug(expected) (actual) should be (expected) + + annotations.foreach { anno => + logger.debug(anno.serialize) + } + + finalState.annotations.toSeq.foreach { anno => + logger.debug(anno.serialize) + } checkAnnotations.foreach { check => (finalState.annotations.toSeq) should contain (check) } |
