Merge branch 'master' into serialization-utils

4 files changed, 139 insertions, 21 deletions

diff --git a/src/test/scala/firrtlTests/FlattenTests.scala b/src/test/scala/firrtlTests/FlattenTests.scala
index 82c3ebdc..468cc1c4 100644
--- a/src/test/scala/firrtlTests/FlattenTests.scala
+++ b/src/test/scala/firrtlTests/FlattenTests.scala
@@ -25,7 +25,7 @@ class FlattenTests extends LowTransformSpec {
     val name = if (parts.size == 1) modName else ComponentName(parts.tail.mkString("."), modName)
     FlattenAnnotation(name)
   }
-  
+
   "The modules inside Top " should "be inlined" in {
      val input =
         """circuit Top :
@@ -55,7 +55,7 @@ class FlattenTests extends LowTransformSpec {
           |    b <= a""".stripMargin
      execute(input, check, Seq(flatten("Top")))
   }
-  
+
   "Two instances of the same module inside Top " should "be inlined" in {
      val input =
         """circuit Top :
@@ -112,14 +112,14 @@ class FlattenTests extends LowTransformSpec {
           |    input a : UInt<32>
           |    output b : UInt<32>
           |    inst i of Inline2
-          |    i.a <= a 
-          |    b <= i.a 
+          |    i.a <= a
+          |    b <= i.a
           |  module Inline1 :
           |    input a : UInt<32>
           |    output b : UInt<32>
           |    inst i of Inline2
-          |    i.a <= a 
-          |    b <= i.a 
+          |    i.a <= a
+          |    b <= i.a
           |  module Inline2 :
           |    input a : UInt<32>
           |    output b : UInt<32>
@@ -147,13 +147,13 @@ class FlattenTests extends LowTransformSpec {
           |    input a : UInt<32>
           |    output b : UInt<32>
           |    inst i of Inline2
-          |    b <= i.a 
-          |    i.a <= a 
+          |    b <= i.a
+          |    i.a <= a
           |  module Inline1 :
           |    input a : UInt<32>
           |    output b : UInt<32>
-          |    inst i of Inline2 
-          |    b <= i.a 
+          |    inst i of Inline2
+          |    b <= i.a
           |    i.a <= a
           |  module Inline2 :
           |    input a : UInt<32>
@@ -179,14 +179,14 @@ class FlattenTests extends LowTransformSpec {
           |    input a : UInt<32>
           |    output b : UInt<32>
           |    inst i of Inline2
-          |    i.a <= a 
-          |    b <= i.a 
+          |    i.a <= a
+          |    b <= i.a
           |  module Inline1 :
           |    input a : UInt<32>
           |    output b : UInt<32>
           |    inst i of Inline2
-          |    i.a <= a 
-          |    b <= i.a 
+          |    i.a <= a
+          |    b <= i.a
           |  module Inline2 :
           |    input a : UInt<32>
           |    output b : UInt<32>
@@ -208,8 +208,8 @@ class FlattenTests extends LowTransformSpec {
           |    input a : UInt<32>
           |    output b : UInt<32>
           |    inst i of Inline2
-          |    b <= i.a 
-          |    i.a <= a 
+          |    b <= i.a
+          |    i.a <= a
           |  module Inline1 :
           |    input a : UInt<32>
           |    output b : UInt<32>
@@ -234,4 +234,50 @@ class FlattenTests extends LowTransformSpec {
          |""".stripMargin
     execute(input, input, Seq.empty)
   }
+
+  "The Flatten transform" should "ignore extmodules" in {
+    val input = """
+      |circuit Top :
+      |  module Top :
+      |    input a : UInt<32>
+      |    output b : UInt<32>
+      |    inst i of Inline
+      |    i.a <= a
+      |    b <= i.b
+      |  module Inline :
+      |    input a : UInt<32>
+      |    output b : UInt<32>
+      |    inst i of ExternalMod
+      |    i.a <= a
+      |    b <= i.b
+      |  extmodule ExternalMod :
+      |    input a : UInt<32>
+      |    output b : UInt<32>
+      |    defname = ExternalMod
+      """.stripMargin
+    val check = """
+      |circuit Top :
+      |  module Top :
+      |    input a : UInt<32>
+      |    output b : UInt<32>
+      |    wire i_a : UInt<32>
+      |    wire i_b : UInt<32>
+      |    inst i_i of ExternalMod
+      |    i_b <= i_i.b
+      |    i_i.a <= i_a
+      |    b <= i_b
+      |    i_a <= a
+      |  module Inline :
+      |    input a : UInt<32>
+      |    output b : UInt<32>
+      |    inst i of ExternalMod
+      |    b <= i.b
+      |    i.a <= a
+      |  extmodule ExternalMod :
+      |    input a : UInt<32>
+      |    output b : UInt<32>
+      |    defname = ExternalMod
+      """.stripMargin
+    execute(input, check, Seq(flatten("Top")))
+  }
 }
diff --git a/src/test/scala/firrtlTests/ParserSpec.scala b/src/test/scala/firrtlTests/ParserSpec.scala
index 711df5ed..4f28e100 100644
--- a/src/test/scala/firrtlTests/ParserSpec.scala
+++ b/src/test/scala/firrtlTests/ParserSpec.scala
@@ -169,6 +169,29 @@ class ParserSpec extends FirrtlFlatSpec {
       Driver.execute(manager)
     }
   }
+
+  "Trailing syntax errors" should "be caught in the parser" in {
+    val input = s"""
+      |circuit Foo:
+      |  module Bar:
+      |    input a: UInt<1>
+      |output b: UInt<1>
+      |    b <- a
+      |
+      |  module Foo:
+      |    input a: UInt<1>
+      |    output b: UInt<1>
+      |    inst bar of Bar
+      |    bar.a <- a
+      |    b <- bar.b
+      """.stripMargin
+    val manager = new ExecutionOptionsManager("test") with HasFirrtlOptions {
+      firrtlOptions = FirrtlExecutionOptions(firrtlSource = Some(input))
+    }
+    a [SyntaxErrorsException] shouldBe thrownBy {
+      Driver.execute(manager)
+    }
+  }
 }
 
 class ParserPropSpec extends FirrtlPropSpec {
diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index 7ea2f03a..cf2ff320 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -267,6 +267,24 @@ class VerilogEmitterSpec extends FirrtlFlatSpec {
     }
   }
 
+  "Initial Blocks" should "be guarded by ifndef SYNTHESIS" in {
+    val input =
+      """circuit Test :
+        |  module Test :
+        |    input clock : Clock
+        |    input reset : AsyncReset
+        |    input in : UInt<8>
+        |    output out : UInt<8>
+        |    reg r : UInt<8>, clock with : (reset => (reset, UInt(0)))
+        |    r <= in
+        |    out <= r
+        """.stripMargin
+    val state = CircuitState(parse(input), ChirrtlForm)
+    val result = (new VerilogCompiler).compileAndEmit(state, List())
+    result should containLines ("`ifndef SYNTHESIS", "initial begin")
+    result should containLines ("end // initial", "`endif // SYNTHESIS")
+  }
+
   "Verilog name conflicts" should "be resolved" in {
     val input =
       """|circuit parameter:
diff --git a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
index e98c1895..eb62c564 100644
--- a/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
+++ b/src/test/scala/firrtlTests/analyses/InstanceGraphTests.scala
@@ -1,12 +1,8 @@
 package firrtlTests.analyses
 
-import java.io._
-import org.scalatest._
-import org.scalatest.prop._
-import org.scalatest.Matchers._
 import firrtl.analyses.InstanceGraph
 import firrtl.graph.DiGraph
-import firrtl.Parser.parse
+import firrtl.WDefInstance
 import firrtl.passes._
 import firrtlTests._
 
@@ -39,6 +35,41 @@ circuit Top :
     getEdgeSet(graph) shouldBe Map("Top" -> Set("Child1", "Child2"), "Child1" -> Set("Child1a", "Child1b"), "Child2" -> Set(), "Child1a" -> Set(), "Child1b" -> Set())
   }
 
+  it should "find hierarchical instances correctly in disconnected hierarchies" in {
+    val input = """
+circuit Top :
+  module Top :
+    inst c of Child1
+  module Child1 :
+    skip
+
+  module Top2 :
+    inst a of Child2
+    inst b of Child3
+    skip
+  module Child2 :
+    inst a of Child2a
+    inst b of Child2b
+    skip
+  module Child2a :
+    skip
+  module Child2b :
+    skip
+  module Child3 :
+    skip
+"""
+
+    val circuit = ToWorkingIR.run(parse(input))
+    val iGraph = new InstanceGraph(circuit)
+    iGraph.findInstancesInHierarchy("Top") shouldBe Seq(Seq(WDefInstance("Top", "Top")))
+    iGraph.findInstancesInHierarchy("Child1") shouldBe Seq(Seq(WDefInstance("Top", "Top"), WDefInstance("c", "Child1")))
+    iGraph.findInstancesInHierarchy("Top2") shouldBe Nil
+    iGraph.findInstancesInHierarchy("Child2") shouldBe Nil
+    iGraph.findInstancesInHierarchy("Child2a") shouldBe Nil
+    iGraph.findInstancesInHierarchy("Child2b") shouldBe Nil
+    iGraph.findInstancesInHierarchy("Child3") shouldBe Nil
+  }
+
   it should "recognize disconnected hierarchies" in {
     val input = """
 circuit Top :