diff options
| author | Jack Koenig | 2019-11-06 16:37:59 -0800 |
|---|---|---|
| committer | mergify[bot] | 2019-11-07 00:37:59 +0000 |
| commit | c450cf974484d4896910c44166481d0849219751 (patch) | |
| tree | eb5c2265f9cd07be496f139d8e567aea3ece7961 /src/test | |
| parent | 954777159d03bd196f6014cd885497c1502ff230 (diff) | |
Add check for multiple sources for same wiring pin (#1191)
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/WiringTests.scala | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/test/scala/firrtlTests/WiringTests.scala b/src/test/scala/firrtlTests/WiringTests.scala index ec69c39f..b2793494 100644 --- a/src/test/scala/firrtlTests/WiringTests.scala +++ b/src/test/scala/firrtlTests/WiringTests.scala @@ -809,4 +809,24 @@ class WiringTests extends FirrtlFlatSpec { val wiringPass = new Wiring(wiSeq) executeTest(input, check, passes :+ wiringPass) } + + it should "error when there are multiple sources for the same pin" in { + val sink = ComponentName("s", ModuleName("Top", CircuitName("Top"))) + val source1 = ComponentName("r", ModuleName("Top", CircuitName("Top"))) + val source2 = ComponentName("r2", ModuleName("Top", CircuitName("Top"))) + val annos = Seq(SourceAnnotation(source1, "pin"), + SourceAnnotation(source2, "pin"), + SinkAnnotation(sink, "pin")) + val input = + """|circuit Top : + | module Top : + | input clock: Clock + | wire s: UInt<5> + | reg r: UInt<5>, clock + | reg r2: UInt<5>, clock + |""".stripMargin + a [WiringException] shouldBe thrownBy { + executeTest(input, "", passes :+ new WiringTransform, annos) + } + } } |
