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2016-11-01Fix Match Error in Check Types on Partial Connect (#359)Jack Koenig
Fixes #329
2016-10-31Fixed Verilog emission of andr, orr, and xorr (#357)Adam Izraelevitz
Fixed Verilog emission reduce ops with efficient implementation
2016-10-30Cleanup fixed point tests (#339)Jack Koenig
Change FixedPointMathSpec tests to use FlatSpec style instead of println Remove other printlns Remove vim comments at end of files
2016-10-30Keep package name + directory structure consistent (#354)Colin Schmidt
* Keep package name + directory structure consistent This annoyed me so heres a PR * fix InferReadWrite references * delete .ConvertFixedToSInt.scala.swo
2016-10-27Wiring (#348)Adam Izraelevitz
Added wiring pass and simple test
2016-10-26Add RawString ExtModule parameter supportjackkoenig
While unsafe, this supports Verilog parameter types. Tests now require Verilator 3.884+ to pass.
2016-10-26Add Support for Parameterized ExtModules and Name Overridejackkoenig
Adds support for Integer, Double/Real, and String parameters in external modules. Also add name field to extmodules so that emitted name can be different from Firrtl name. This is important because parameterized extmodules will frequently have differing IO even though they need to be emitted as instantiating the same Verilog module.
2016-10-26Add ExtModule Testsjackkoenig
2016-10-26Improve integration test API and add support for Verilog resourcesjackkoenig
Change integration tests to be classes that extend abstract classes. This allows them to be run in parallel. Also expand API to support Verilog resources in integration tests.
2016-10-18Create a simple system for executions and command line parameters (#337)Chick Markley
Create a simple system for executions and command line parameters New model for tracking parameters and having those parameters register scopt command to allow the parameters to be set by command line args. Create composable forms of the these parameters to allow separate elements of the chisel3 toolchain to combine these parameters Create execution return structures that simplify return values to earlier toolchain elements
2016-10-17Reorganized memory blackboxing (#336)Adam Izraelevitz
* Reorganized memory blackboxing Moved to new package memlib Added comments Moved utility functions around Removed unused AnnotateValidMemConfigs.scala * Fixed tests to pass * Use DefAnnotatedMemory instead of AppendableInfo * Broke passes up into simpler passes AnnotateMemMacros -> (ToMemIR, ResolveMaskGranularity) UpdateDuplicateMemMacros -> (RenameAnnotatedMemoryPorts, ResolveMemoryReference) * Fixed to make tests run * Minor changes from code review * Removed vim comments and renamed ReplSeqMem
2016-10-17Add fixed point type (#322)Adam Izraelevitz
* WIP: Adding FixedType to Firrtl proper Got simple example running through width inference Checks should be ok Need to look into FixedLiteral more * Added simple test for fixed types * Added asFixedPoint to primops * Added tail case for FixedType * Added ConvertFixedToSInt.scala Added pass to MiddleToLowerFirrtl transform * Replace AsFixedType with AsSInt in fixed removal * Bugfix: constant from asFixed not deleted * Added unit test for bulk connect * Fixed partial connect bug #241 * Fixed missing case for FixedPoint in legalizeConnect * Add FixedMathSpec that demonstrates some problems with FixedPointMath * Fixed test and ConvertToSInt to pass. Negative binary points not easily supported, needs much more time to implement. * Refactored checking neg widths Make checking for negative binary points easier * Added tests for inferring many FixedType ops shl, shr, cat, bits, head, tail, setbp, shiftbp * Handle bpshl, bpshr, bpset in ConvertFixedToSInt Changed name from shiftbp -> bpshl, bpshr Change name from setbp -> bpset Added more tests * Added set binary point test that fails * Added simple test for zero binary point * gitignore fixes for antlr intermediate dir and intellij dir * removed unused imports retool the fixed point with zero binary point test * simplified example of inability to set binary point to zero * Temporary fix for zero-width binary point This fix allows for all widths to be zero, but since this is a feature I am working on next, I'm not going to bother with a more stringent check. * change version for dsp tools * Removed extra temporary file * Fixed merge bug * Fixed another merge bug * Removed commented out/unrelated files * Removed snake case
2016-10-07Add test for Firrtl mems with no ports (#327)Jack Koenig
2016-09-26add CInferMDirSpecDonggyu Kim
2016-09-26Added max width check to dshl shift amount (#318)Adam Izraelevitz
Address #297
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
* Spec features added: AnalogType and Attach AnalogType(width: Width): - Concrete syntax: wire x: AnalogType<10> - New groundtype, very restricted in use cases. - Can only declare ports and wires with Analog type - Analog types are never equivalent, thus if x and y have Analog types: x <= y is never legal. Attach(info: Info, source: Expression, exprs: Seq[Expression]): - Concrete syntax: attach x to (y, z) - New statement - Source can be any groundtyped expression (UInt, SInt, Analog, Clock) - Exprs must have an Analog type reference an instance port - Source and exprs must have identical widths Included WDefInstanceConnector to enable emission of Verilog inout Should be mostly feature complete. Need to update spec if PR gets accepted. * Fixed bug where invalidated ports aren't handled * Bugfix for VerilogPrep Intermediate wires for invalidated instance ports were not invalidated * Bugfix: calling create_exp with name/tpe Returns unknown gender, which was passing through Caused temporary wire to not be declared Because Verilog is dumb, undeclared wires are assumed to be 1bit signals * Addressed donggyukim's style comments * Reworked pass to only allow analog types in attach Restrict source to be only wire or port kind Much simpler implementation, almost identical functionality Clearer semantics (i think?) * Fixup bugs from pulling in new changes from master * comments for type eqs and small style fixes
2016-09-22Fixed width inference for add, sub (#312)Adam Izraelevitz
Fixes #308 Fixes #193
2016-09-21Fix clock connections in InferReadWrite (#310)Donggyu
2016-09-21refactor AnnotateMemMacrosDonggyu Kim
2016-09-21refactor InferReadWriteDonggyu Kim
2016-09-14Added Rob.fir for regression testing (#258)Donggyu
2016-09-14fix enable signal inferecne for smems' read ports (#289)Donggyu
2016-09-14Fixed infinite loop for finding connect origin in ReplSeqMem (#300)Angie Wang
* Addressed the fact that a node can be connected to itself (updating reg)
2016-09-12Add LegalizeSpec for testing Verilog Legalization passJack
2016-09-12Added test to check invalid bug was fixedazidar
2016-09-12Bug fix -- remove all empty expressions after ReplSeqMem passes (#294)Angie Wang
* Bug fix -- remove all empty expressions after ReplSeqMem passes * Added test to make sure ReplSeqMem can handle BundleType SMem (EmptyExpression leakage)
2016-09-08Remove brittle ReplSeqMemTestjackkoenig
This test is breaks with any minor change to code generation. It should be replaced with a more robust test.
2016-09-08remove Utils.{AND, OR, NOT, EQV}Donggyu Kim
hidden const props not desirable
2016-09-08clean up ExpandWhensDonggyu Kim
2016-09-07refactor checksDonggyu Kim
2016-09-06Address style feedback and add tests for getConnectOrigin utilityAngie
2016-09-06Expanded annotations for valid memory sizesAngie
2016-09-06Added simple unit test for ReplSeqMemAngie
2016-08-25emit wires instead of registers for invalid randomizationHoward Mao
Before, the verilog emitter would connect registers to the invalid ports and use random initialization on the generated registers. It is better to generate wires instead and use random assignment on the wires.
2016-08-25update verilog generation testHoward Mao
2016-08-16add test case for clock type connection (#239)mwachs5
2016-08-04Addd check: bits, tail, head arg widthazidar
2016-08-03fixes small mistakes in serialize (#216)Donggyu
2016-08-02Merge pull request #203 from ucb-bar/fix_mem_inferAdam Izraelevitz
Fix mem infer
2016-08-02make infer readwrite ports optionalDonggyu Kim
turned on with '--inferRW <circuit name>'
2016-08-02Merge pull request #214 from ucb-bar/fix-thread-unsafetyAdam Izraelevitz
Fix use of global state in instance loop checking
2016-08-02Merge pull request #211 from ucb-bar/fix-subaccessAdam Izraelevitz
Refactor RemoveAccesses and fix bug #210.
2016-08-02Fix use of global state in instance loop checkingjackkoenig
Also increase sensitivity of thread safety checking Fixes #159
2016-08-01Refactor RemoveAccesses and fix bug #210.azidar
Added corresponding unit test.
2016-08-01Fix StringSpec generators to only choose from valid values.Jack Koenig
The old almost equivalent syntax gives the same result but can cause the test to fail if too many invalid values are thrown away.
2016-07-27Fixed compilation error using old annotationsazidar
2016-07-27Reworked annotation system. Added tenacity and permissibilityAdam Izraelevitz
Conflicts: src/main/scala/firrtl/Compiler.scala src/main/scala/firrtl/LoweringCompilers.scala src/main/scala/firrtl/passes/Inline.scala src/test/scala/firrtlTests/AnnotationTests.scala src/test/scala/firrtlTests/InlineInstancesTests.scala
2016-07-27Merge pull request #198 from ucb-bar/add-chirrtl-checkAdam Izraelevitz
Added a Chirrtl check for undeclared wires, etc.
2016-07-25Detects and flags cyclic module loopschick
2016-07-21Added a Chirrtl check for undeclared wires, etc.azidar
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