diff options
| author | Howard Mao | 2016-08-25 20:06:43 -0700 |
|---|---|---|
| committer | Howard Mao | 2016-08-25 20:06:48 -0700 |
| commit | a2af16c1fb1f5166eab34188df9944012da3cbc3 (patch) | |
| tree | f92b7d24794c56be31bf5d9ab3859537e3debd4a /src/test | |
| parent | e69d44fc944b5d93c852d54911ce7cf61abb6dd1 (diff) | |
emit wires instead of registers for invalid randomization
Before, the verilog emitter would connect registers to the invalid ports
and use random initialization on the generated registers.
It is better to generate wires instead and use random assignment on the
wires.
Diffstat (limited to 'src/test')
| -rw-r--r-- | src/test/scala/firrtlTests/CompilerTests.scala | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala index 5b154327..2eab6e0f 100644 --- a/src/test/scala/firrtlTests/CompilerTests.scala +++ b/src/test/scala/firrtlTests/CompilerTests.scala @@ -106,7 +106,10 @@ circuit Top : b <= a """ val check = Seq( - "`ifdef RANDOMIZE_ASSIGN", + "`ifdef RANDOMIZE_GARBAGE_ASSIGN", + "`define RANDOMIZE", + "`endif", + "`ifdef RANDOMIZE_INVALID_ASSIGN", "`define RANDOMIZE", "`endif", "`ifdef RANDOMIZE_REG_INIT", |