From a2af16c1fb1f5166eab34188df9944012da3cbc3 Mon Sep 17 00:00:00 2001
From: Howard Mao
Date: Thu, 25 Aug 2016 20:06:43 -0700
Subject: emit wires instead of registers for invalid randomization

Before, the verilog emitter would connect registers to the invalid ports
and use random initialization on the generated registers.

It is better to generate wires instead and use random assignment on the
wires.
---
 src/test/scala/firrtlTests/CompilerTests.scala | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index 5b154327..2eab6e0f 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -106,7 +106,10 @@ circuit Top :
     b <= a
 """
    val check = Seq(
-      "`ifdef RANDOMIZE_ASSIGN",
+      "`ifdef RANDOMIZE_GARBAGE_ASSIGN",
+      "`define RANDOMIZE",
+      "`endif",
+      "`ifdef RANDOMIZE_INVALID_ASSIGN",
       "`define RANDOMIZE",
       "`endif",
       "`ifdef RANDOMIZE_REG_INIT",
-- 
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