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AgeCommit message (Expand)Author
2016-11-01Fix Match Error in Check Types on Partial Connect (#359)Jack Koenig
2016-10-31Fixed Verilog emission of andr, orr, and xorr (#357)Adam Izraelevitz
2016-10-30Cleanup fixed point tests (#339)Jack Koenig
2016-10-30Keep package name + directory structure consistent (#354)Colin Schmidt
2016-10-27Wiring (#348)Adam Izraelevitz
2016-10-26Add RawString ExtModule parameter supportjackkoenig
2016-10-26Add Support for Parameterized ExtModules and Name Overridejackkoenig
2016-10-26Add ExtModule Testsjackkoenig
2016-10-26Improve integration test API and add support for Verilog resourcesjackkoenig
2016-10-18Create a simple system for executions and command line parameters (#337)Chick Markley
2016-10-17Reorganized memory blackboxing (#336)Adam Izraelevitz
2016-10-17Add fixed point type (#322)Adam Izraelevitz
2016-10-07Add test for Firrtl mems with no ports (#327)Jack Koenig
2016-09-26add CInferMDirSpecDonggyu Kim
2016-09-26Added max width check to dshl shift amount (#318)Adam Izraelevitz
2016-09-25Spec features added: AnalogType and Attach (#295)Adam Izraelevitz
2016-09-22Fixed width inference for add, sub (#312)Adam Izraelevitz
2016-09-21Fix clock connections in InferReadWrite (#310)Donggyu
2016-09-21refactor AnnotateMemMacrosDonggyu Kim
2016-09-21refactor InferReadWriteDonggyu Kim
2016-09-14Added Rob.fir for regression testing (#258)Donggyu
2016-09-14fix enable signal inferecne for smems' read ports (#289)Donggyu
2016-09-14Fixed infinite loop for finding connect origin in ReplSeqMem (#300)Angie Wang
2016-09-12Add LegalizeSpec for testing Verilog Legalization passJack
2016-09-12Added test to check invalid bug was fixedazidar
2016-09-12Bug fix -- remove all empty expressions after ReplSeqMem passes (#294)Angie Wang
2016-09-08Remove brittle ReplSeqMemTestjackkoenig
2016-09-08remove Utils.{AND, OR, NOT, EQV}Donggyu Kim
2016-09-08clean up ExpandWhensDonggyu Kim
2016-09-07refactor checksDonggyu Kim
2016-09-06Address style feedback and add tests for getConnectOrigin utilityAngie
2016-09-06Expanded annotations for valid memory sizesAngie
2016-09-06Added simple unit test for ReplSeqMemAngie
2016-08-25emit wires instead of registers for invalid randomizationHoward Mao
2016-08-25update verilog generation testHoward Mao
2016-08-16add test case for clock type connection (#239)mwachs5
2016-08-04Addd check: bits, tail, head arg widthazidar
2016-08-03fixes small mistakes in serialize (#216)Donggyu
2016-08-02Merge pull request #203 from ucb-bar/fix_mem_inferAdam Izraelevitz
2016-08-02make infer readwrite ports optionalDonggyu Kim
2016-08-02Merge pull request #214 from ucb-bar/fix-thread-unsafetyAdam Izraelevitz
2016-08-02Merge pull request #211 from ucb-bar/fix-subaccessAdam Izraelevitz
2016-08-02Fix use of global state in instance loop checkingjackkoenig
2016-08-01Refactor RemoveAccesses and fix bug #210.azidar
2016-08-01Fix StringSpec generators to only choose from valid values.Jack Koenig
2016-07-27Fixed compilation error using old annotationsazidar
2016-07-27Reworked annotation system. Added tenacity and permissibilityAdam Izraelevitz
2016-07-27Merge pull request #198 from ucb-bar/add-chirrtl-checkAdam Izraelevitz
2016-07-25Detects and flags cyclic module loopschick
2016-07-21Added a Chirrtl check for undeclared wires, etc.azidar
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