Address style feedback and add tests for getConnectOrigin utility

1 files changed, 46 insertions, 1 deletions

diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index 57a274c2..54ef6003 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -17,6 +17,51 @@ class ReplSeqMemSpec extends SimpleTransformSpec {
     new EmitFirrtl(writer)
   )
 
+  "ReplSeqMem Utility -- getConnectOrigin" should 
+      "determine connect origin across nodes/PrimOps even if ConstProp isn't performed" in {
+    def checkConnectOrigin(hurdle: String, origin: String) = {
+      val input = s"""
+circuit Top :
+  module Top :
+    input a: UInt<1>
+    input b: UInt<1>
+    input e: UInt<1>
+    output c: UInt<1>
+    output f: UInt<1>
+    node d = $hurdle
+    c <= d
+    f <= c
+""".stripMargin
+
+      val circuit = InferTypes.run(ToWorkingIR.run(parse(input)))
+      val m = circuit.modules.head.asInstanceOf[ir.Module]
+      val connects = AnalysisUtils.getConnects(m)
+      val calculatedOrigin = AnalysisUtils.getConnectOrigin(connects,"f").serialize 
+      require(calculatedOrigin == origin, s"getConnectOrigin returns incorrect origin $calculatedOrigin !")
+    }
+
+    val tests = List(
+      """mux(a, UInt<1>("h1"), UInt<1>("h0"))""" -> "a",
+      """mux(UInt<1>("h1"), a, b)""" -> "a",
+      """mux(UInt<1>("h0"), a, b)""" -> "b",
+      "mux(b, a, a)" -> "a",
+      """mux(a, a, UInt<1>("h0"))""" -> "a",
+      "mux(a, b, e)" -> "mux(a, b, e)",
+      """or(a, UInt<1>("h1"))""" -> """UInt<1>("h1")""",
+      """and(a, UInt<1>("h0"))""" -> """UInt<1>("h0")""",
+      """UInt<1>("h1")""" -> """UInt<1>("h1")""",
+      "asUInt(a)" -> "a",
+      "asSInt(a)" -> "a",
+      "asClock(a)" -> "a",
+      "a" -> "a",
+      "or(a, b)" -> "or(a, b)",
+      "bits(a, 0, 0)" -> "a"
+    )
+
+    tests.foreach{ case(hurdle, origin) => checkConnectOrigin(hurdle, origin) }
+
+  }
+
   "ReplSeqMem" should "generate blackbox wrappers (no wmask, r, w ports)" in {
     val input = """
 circuit sram6t :
@@ -116,7 +161,7 @@ circuit sram6t :
     val writer = new java.io.StringWriter
     execute(writer, aMap, input, check)
     val confOut = read(confLoc)
-    require(confOut==checkConf,"Conf file incorrect!")
+    require(confOut==checkConf, "Conf file incorrect!")
     (new java.io.File(confLoc)).delete()
   }
 }