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AgeCommit message (Expand)Author
2017-12-19Make toNamed invert serialize (#709)Schuyler Eldridge
2017-12-12Add RemoveWires transformJack Koenig
2017-11-28Have DedupModules report renamingJack
2017-11-28Refactor RenameMap to rename Components if their Module is renamedJack
2017-11-16Move digraph exceptions out of digraph class (#688)Albert Magyar
2017-11-10Make digraph methods deterministic (#653)Albert Magyar
2017-11-08Add InfoSpec for checking Info propagationJack Koenig
2017-11-08Add FirrtlCheckers and scalatest helpers for testingJack Koenig
2017-10-31Fix bug emitting and reparsing ExtModule String parameters (#675)Jack Koenig
2017-09-30Make ReplaceAccesses optimize multi-dimensional accesses (#665)Albert Magyar
2017-09-30Fixed zero width cat but (#651)Adam Izraelevitz
2017-09-29StringLit.verilogEscape should support all printable ASCII chars (#668)Jack Koenig
2017-09-29Namespace - only save suffix for temp names (#667)Jack Koenig
2017-09-22Fix string lit (#663)Jack Koenig
2017-09-19Create way of collecting program arguments in Driver (#659)Chick Markley
2017-09-06Write tests on multi-rooted circuits for ConstPropEdward Wang
2017-09-05Add InstanceGraph testsEdward Wang
2017-08-23Reorder port and wire assignments in Verilog (#641)Adam Izraelevitz
2017-08-14Constant propagation across module boundaries (#633)Jack Koenig
2017-08-04bug fix for cases when we want to flatten a module in which a module is insta...Andrey Ayupov
2017-08-01DCE for IsInvalid (#629)Donggyu
2017-07-26Flatten transformation (#631)Andrey Ayupov
2017-07-17do not swap wire names with node namesDonggyu Kim
2017-07-17Fix ConstProp bug where multiple names would swap with oneJack Koenig
2017-07-14Fix bug in DiGraph.reverse on an graph with one vertex, no edges (#628)Jack Koenig
2017-07-06Fixed inability to disable combo loop check (#619)Chick Markley
2017-06-29ConstProp registers that are only connected to or reset to a consantJack Koenig
2017-06-29Add test for padding constant connections to wires in ConstPropJack Koenig
2017-06-29Preserve "better" names in Constant PropagationJack Koenig
2017-06-28Make Constant Propagation respect dontTouchJack Koenig
2017-06-28Promote ConstProp to a transformJack Koenig
2017-06-28[Testing] Clean up SimpleTransformSpec execute methodsJack Koenig
2017-06-28[Testing] Have SimpleTransformSpec mix in FirrtlMatchersJack Koenig
2017-06-27Emitting reg update mux tree, only walk netlist for wires and nodesJack Koenig
2017-06-26Add support for wires in ConstPropJack Koenig
2017-06-21Add --no-dce command-line option to skip DCEJack Koenig
2017-06-13Make ExpandWhens delete 'is invalid' for attached Analog componentsJack Koenig
2017-06-13Style changes to ExpandWhensSpecJack Koenig
2017-06-12Add option to disable combinational loop detectionJack Koenig
2017-06-12Move CheckCombLoops from passes/ to transforms/Jack Koenig
2017-06-12Fixes a typo in the verilog `elsif code generation (#603)Shreesha Srinath
2017-05-27Prep for Scala 2.12 (#557)Jim Lawson
2017-05-18Upgrade Logging facility (#488)Chick Markley
2017-05-17Make sure not to DCE input-only extmodules unless specified (#590)Jack Koenig
2017-05-12Bugfix: renaming instance ports was broken. (#588)Adam Izraelevitz
2017-05-11Improved Global Dead Code Elimination (#549)Jack Koenig
2017-05-10Update rename2 (#478)Adam Izraelevitz
2017-05-03Add checks on register clock and reset types (#33) (#553)Albert Magyar
2017-05-03Add test for source locators on multi-line reset registers (#554)Jack Koenig
2017-04-18"Scope" test resource (top.cpp). (#398)Jim Lawson
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